Analog-to-digital converter with bandpass noise transfer function

Patent metadata

Field	Value
Publication number	US-9722746-B2
Application number	US-201615165088-A
Country	US
Kind code	B2
Filing date	May 26, 2016
Priority date	Sep 22, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

Methods and apparatus for providing bandpass analog to digital conversion (ADC) in RF receiver circuitry of a wireless-communication device. The bandpass ADC includes first noise-shaping successive approximation register (NS-SAR) circuitry arranged in a first path and second NS-SAR circuitry arranged in a second path parallel to the first path, wherein the first and second NS-SAR circuitries are configured to alternately sample an analog input voltage at a particular sampling rate and to output a digital voltage at the particular sampling rate.

First claim

What is claimed is:

1. A bandpass analog-to-digital converter (ADC) for use in RF receiver circuitry of a wireless communication device, the bandpass ADC comprising:
first noise-shaping successive approximation register (NS-SAR) circuitry arranged in a first path; and
second NS-SAR circuitry arranged in a second path parallel to the first path, wherein the first and second NS-SAR circuitries are configured to alternately sample an analog input voltage at a particular sampling rate.

2. The bandpass ADC of claim 1 , wherein each of the first NS-SAR circuitry and the second NS-SAR circuitry includes:
a capacitor digital to analog converter (DAC) onto which the analog input voltage is sampled;
noise-shaping circuitry arranged to process a residue voltage output from the capacitor DAC; and
an SAR comparator arranged to receive the output of the noise-shaping circuitry.

3. The bandpass ADC of claim 2 , wherein the noise-shaping circuitry comprises a low-noise amplifier and loop filter circuitry, wherein the low-noise amplifier is arranged to amplify the residue voltage output from the capacitor DAC, and wherein the loop filter circuitry is arranged between the output of the low-noise amplifier and an input of the SAR comparator.

4. The bandpass ADC of claim 3 , wherein the loop filter circuitry comprises:
low-pass loop filter circuitry;
first inverter circuitry arranged between the low-noise amplifier and an input of the low-pass loop filter circuitry; and
second inverter circuitry arranged between an output of the low-pass loop filter circuitry and the input of the SAR comparator.

5. The bandpass ADC of claim 4 , wherein each of the first inverter circuitry and the second inverter circuitry comprise a transmission gate switch.

6. The bandpass ADC of claim 3 , wherein the low-noise amplifier is configured to be powered on only during transfer of the residual voltage to the loop filter circuitry.

7. The bandpass ADC of claim 2 , wherein the first NS-SAR circuitry includes a feedback path from the output of the SAR comparator to the capacitor DAC.

8. The bandpass ADC of claim 2 , wherein the SAR comparator includes a first input and a second input, wherein the SAR comparator is arranged to receive the output of the noise-shaping circuitry at the first input and output of the capacitor DAC at the second input.

9. The bandpass ADC of claim 1 , further comprising a first switch arranged at the output of the first NS-SAR circuitry and a second switch arranged at the output of the second NS-SAR circuitry, wherein the first switch and the second switch are configured to alternately sample the output of the first and second NS-SAR circuitries at the particular sampling frequency to generate digital output.

10. A wireless communication device including receiver circuitry configured to process an input signal comprising an intra-band non-contiguous carrier aggregated RF signal with two component carriers, the receiver circuitry comprising:
local oscillator circuitry configured to downconvert the input signal;
low-pass filter circuitry coupled to the output of the local oscillator circuitry;
bandpass analog-to-digital converter (ADC) circuitry coupled to the output of the low-pass filter circuitry and configured to sample the filtered output of the low-pass filter circuitry at a sampling frequency proportional to an intermediate frequency of the receiver circuitry; and
digital circuitry coupled to the output of the bandpass ADC circuitry, wherein the digital circuitry is configured to downconvert the output of the bandpass ADC circuitry to baseband in the digital domain.

11. The wireless communication device of claim 10 , wherein the local oscillator circuitry is further configured to downconvert the input signal using a local oscillator frequency equal to a frequency between center frequencies of the two component carriers.

12. The wireless communication device of claim 10 , wherein the digital circuitry comprises a plurality of mixers configured to process the output of the bandpass ADC circuitry at different timings to downconvert the bandpass ADC output to baseband.

13. The wireless communication device of claim 10 , further comprising wideband RF amplification circuitry arranged to amplify the input signal prior to downconverting the input signal with the local oscillator circuitry.

14. The wireless communication device of claim 10 , wherein the bandpass ADC circuitry comprises a plurality of noise-shaping successive approximation register (NS-SAR) circuitry paths arranged in parallel.

15. The wireless communication device of claim 14 , wherein at least one of the NS-SAR circuitry paths comprises:
a capacitor digital-to-analog converter (DAC) onto which an analog input voltage is sampled;
noise-shaping circuitry arranged to process a residue voltage output from the capacitor DAC; and
an SAR comparator arranged to receive the output of the noise-shaping circuitry.

16. A method of converting an analog input voltage to a digital voltage, the method comprising:
alternately sampling the analog input voltage onto a first capacitor digital to analog converter (DAC) and a second capacitor DAC;
processing, using first noise-shaping circuitry, a residue voltage output from the first capacitor DAC to produce a first noise-shaped signal;
processing, using second noise-shaping circuitry, a residue voltage output from the second capacitor DAC to produce a second noise-shaped signal; and
outputting the digital voltage based, at least in part, on the first noise-shaped signal and/or the second noise-shaped signal.

17. The method of claim 16 , wherein processing the residue voltage output from the first capacitor DAC comprises:
amplifying the residue voltage;
inverting the amplified residue voltage;
filtering the inverted residue voltage; and
inverting the filtered residue voltage to produce the first noise-shaped signal.

18. The method of claim 17 , wherein filtering the inverted residue voltage comprises filtering the inverted residue voltage using a low-pass loop filter.

19. The method of claim 16 , further comprising:
comparing the first noise-shaped signal to a main output from the first capacitor DAC to produce a first compared signal;
comparing the second noise-shaped signal to a main output from the second capacitor DAC to produce a second compared signal; and
wherein outputting the digital voltage comprises alternately sampling the first compared signal and the second compared signal to output the digital voltage.

20. The method of claim 19 , further comprising:
providing feedback based on the first compared signal to the first capacitor DAC.

Assignees

• Mediatek Inc

Inventors

• Ho Stacy
• Tseng Wei-Hsin

Classifications

• H04L27/2647

  Arrangements specific to the receiver only (equalisation H04L27/01) · CPC title

• H04B1/10

  Means associated with receiver for limiting or suppressing noise or interference · CPC title

• H04B1/0075

  using different intermediate frequencied for the different bands · CPC title

• H03M3/47

  using time-division multiplexing · CPC title

• H03M3/426

  the quantiser being a successive approximation type analogue/digital converter · CPC title