Technologies for ethernet link robustness for deep sleep low power applications

Patent metadata

Field	Value
Publication number	US-9722717-B2
Application number	US-201414574482-A
Country	US
Kind code	B2
Filing date	Dec 18, 2014
Priority date	Dec 18, 2014
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

Technologies for robust data transmission include a network port logic having a physical coding sublayer (PCS). The PCS may transmit a series of rapid alignment markers (RAMs) to a link partner, with each RAM indicative of a counter value. The PCS transitions to a sleep state if the counter value equals two and a low power idle (LPI) command is set by an upper-layer client. The PCS transitions to an active state if the counter value equals one and the LPI command is not set. The PCS may receive a low power idle symbol (LI) from the link partner and start a guard timer in response to receipt of the LI symbol. The PCS transitions to a sleep state if the guard timer expires and transitions to the active state if data other than LI is received prior to expiration of the guard timer. Other embodiments are described and claimed.

First claim

The invention claimed is:

1. A network port logic for low-power data communication, the network port logic comprising:
a physical coding sublayer (PCS) logic to:
transmit, during a wake state, a plurality of rapid alignment markers to a remote link partner via a physical link, wherein each rapid alignment marker is indicative of a corresponding counter value that is selected from a sequence of values including a first counter value, a last counter value, and a next-to-last counter value;
determine, during the wake state, whether the counter value of a first rapid alignment marker of the plurality of rapid alignment markers equals the next-to-last counter value and whether a low power idle command is set in response to transmission of the first rapid alignment marker; and
transition from the wake state to a sleep state in response to a determination that the counter value of the first rapid alignment marker equals the next-to-last counter value and the low power idle command is set.

2. The network port logic of claim 1 , wherein the PCS logic is further to:
determine, during the wake state, whether the counter value of the first rapid alignment marker equals the last counter value in response to transmission of the first rapid alignment marker; and
transition from the wake state to an active state in response to a determination that the counter value of the first rapid alignment marker equals the last counter value.

3. The network port logic of claim 2 , wherein the next-to-last counter value equals two and the last counter value equals one.

4. The network port logic of claim 1 , wherein the PCS logic is further to:
receive, in a receiver active state, first data from the remote link partner via the physical link;
determine, in the receiver active state, whether the first data includes a low-power idle code;
transition from the receiver active state to a receiver timer state in response to a determination that the first data includes the low-power idle code;
start a guard timer in response to a transition to the receiver timer state;
receive, in the receiver timer state, second data from the remote link partner via the physical link;
determine, in the receiver timer state, whether the second data includes the low-power idle code; and
transition from the receiver timer state to a receiver sleep state in response to expiration of the guard timer and a determination that the second data includes the low-power idle code.

5. The network port logic of claim 4 , wherein the PCS logic is further to transition from the receiver timer state to the receiver active state in response to a determination that the second data does not include the low-power idle code.

6. The network port logic of claim 1 , wherein the physical link comprises a 40-gigabit copper cable connection or a 40-gigabit backplane connection, and wherein the physical link comprises four physical lanes.

7. The network port logic of claim 1 , wherein the physical link comprises a 100-gigabit copper cable connection, and wherein the physical link comprises 4 physical lanes or 10 physical lanes.

8. A network port logic for low-power data communication, the network port logic comprising:
a physical coding sublayer (PCS) logic to:
receive, in an active state, first data from a remote link partner via a physical link;
determine, in the active state, whether the first data includes a low-power idle code;
transition from the active state to a timer state in response to a determination that the first data includes the low-power idle code;
start a guard timer in response to a transition to the timer state;
receive, in the timer state, second data from the remote link partner via the physical link;
determine, in the timer state, whether the second data includes the low-power idle code; and
transition from the timer state to a sleep state in response to expiration of the guard timer and a determination that the second data includes the low-power idle code.

9. The network port logic of claim 8 , wherein the guard timer specifies a delay of at least 147 nanoseconds.

10. The network port logic of claim 8 , wherein the guard timer specifies a delay of at least 247 nanoseconds.

11. The network port logic of claim 8 , wherein the guard timer specifies a delay of at least 500 nanoseconds.

12. The network port logic of claim 8 , wherein the PCS logic is further to transition from the timer state to the active state in response to a determination that the second data does not include the low-power idle code.

13. One or more non-transitory, computer-readable storage media comprising a plurality of instructions that in response to being executed cause a computing device to:
transmit, during a wake state, a plurality of rapid alignment markers to a remote link partner via a physical link, wherein each rapid alignment marker is indicative of a corresponding counter value that is selected from a sequence of values including a first counter value, a last counter value, and a next-to-last counter value;
determine, during the wake state, whether the counter value of a first rapid alignment marker of the plurality of rapid alignment markers equals the next-to-last counter value and whether a low power idle command is set in response to transmitting the first rapid alignment marker; and
transition from the wake state to a sleep state in response to determining the counter value of the first rapid alignment marker equals the next-to-last counter value and the low power idle command is set.

14. The one or more non-transitory, computer-readable storage media of claim 13 , further comprising a plurality of instructions that in response to being executed cause the computing device to:
determine, during the wake state, whether the counter value of the first rapid alignment marker equals the last counter value in response to transmitting the first rapid alignment marker; and
transition from the wake state to an active state in response to determining the counter value of the first rapid alignment marker equals the last counter value.

15. The one or more non-transitory, computer-readable storage media of claim 14 , wherein the next-to-last counter value equals two and the last counter value equals one.

16. The one or more non-transitory, computer-readable storage media of claim 13 , further comprising a plurality of instructions that in response to being executed cause the computing device to:
receive, in a receiver active state, first data from the remote link partner via the physical link;
determine, in the receiver active state, whether the first data includes a low-power idle code;
transition from the receiver active state to a receiver timer state in response to determining the first data includes the low-power idle code;
start a guard timer in response to transitioning to the receiver timer state;
receive, in the receiver timer state, second data from the remote link partner via the physical link;
determine, in the receiver timer state, whether the second data includes the low-power idle code; and
transition from the receiver timer state to a receiver sleep state in response to expiration of the guard timer and determining that the second data includes the low-power idle code.

17. The one or more non-transitory, computer-readable storage media of claim 16 , further comprising a plurality of instructions that in response to being executed cause the computing device to:
transition from the receiver timer state to the receiver active state in response to determining that the second data does not include the low-po

Assignees

• Intel Corp

Inventors

• Landau Yoni
• Benhamou Assaf
• Ran Adee O

Classifications

• H04L7/041

  using special codes as synchronising signal · CPC title

• H04L2007/045

  Fill bit or bits, idle words · CPC title

• H04J3/0658 Primary

  Clock or time synchronisation among packet nodes · CPC title

• H04L12/12

  Arrangements for remote connection or disconnection of substations or of equipment thereof · CPC title

• Y02B60/35

  Cross-Sectional Technologies · mapped topic