Periodic signal generation circuit and semiconductor system including the same

Patent metadata

Field	Value
Publication number	US-9722583-B2
Application number	US-201514878922-A
Country	US
Kind code	B2
Filing date	Oct 8, 2015
Priority date	Aug 20, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A semiconductor system may include a first semiconductor device configured to output a command and receive data. The semiconductor system may include a second semiconductor device configured to generate a periodic signal, the periodic signals periodically toggled in response to the command, output the data in response to the periodic signal, and discharge the charges of an internal node if the periodic signal is not toggled during a predetermined section.

First claim

What is claimed is:

1. A periodic signal generation circuit, comprising:
an oscillator configured to generate a periodic signal toggled based on an amount of charge of an internal node in response to an enable signal and discharge the charge of the internal node in response to a reset signal;
a detection signal generation unit configured to detect a toggling period of the periodic signal and generate a detection signal, the detection signal is enabled if the periodic signal is not toggled during a predetermined section; and
a reset signal generation unit configured to generate and enable the reset signal in response to the detection signal,
wherein the reset signal is enabled when a level of the detection signal is higher than a target voltage.

2. The periodic signal generation circuit of claim 1 , wherein the oscillator comprises:
a buffer unit configured to generate the periodic signal toggled based on the amount of charges of the internal node in response to the enable signal and the periodic signal; and
a first charge discharge unit configured to discharge the charges of the internal node in response to the reset signal.

3. The periodic signal generation circuit of claim 2 , wherein the buffer unit comprises:
a first logic element configured to invert and buffer the periodic signal in response to the enable signal and output the inverted and buffered signal to a first internal node;
a second logic element configured to invert and buffer the signal of the first internal node and output the inverted and buffered signal; and
a third logic element configured to generate the periodic signal by inverting and buffering the output signal of the second logic element.

4. The periodic signal generation circuit of claim 3 , wherein the first logic element includes a NAND gate configured to receive the periodic signal and the enable signal, and output a resultant signal to the first internal node.

5. The periodic signal generation circuit of claim 3 , wherein the first logic element includes an inverter configured to be turned on when the enable signal is enabled and to receive the periodic signal and output a resultant signal to the first internal node.

6. The periodic signal generation circuit of claim 1 , wherein the detection signal generation unit comprises:
a comparison unit configured to compare the period signal with a reference voltage and generate a comparison signal; and
a detection signal output unit configured to generate the detection signal having a level increased from a level of the ground voltage and generate the detection signal having the level of the ground voltage in response to the comparison signal.

7. The periodic signal generation circuit of claim 6 , wherein the detection signal output unit comprises:
a charge supply unit disposed between a terminal for a power supply voltage and a second internal node and configured to supply charges from the terminal for the power supply voltage to the second internal node based on an internal resistance value; and
a second charge discharge unit electrically coupled between the second internal node and a terminal for the ground voltage and configured to discharge charges of the second internal node in response to the comparison signal.

8. The periodic signal generation circuit of claim 7 , wherein the charge supply unit comprises:
a capacitor electrically coupled between the terminal for the power supply voltage and the second internal node; and
a resistor electrically coupled between the terminal for the power supply voltage and the second internal node and coupled to the capacitor in parallel.

9. The periodic signal generation circuit of claim 7 , wherein the charge supply unit comprises a PMOS transistor having a source coupled to the power supply voltage, a gate coupled to the power supply voltage and the source, and a drain coupled to the second internal node.

10. The periodic signal generation circuit of claim 7 , wherein the charge supply unit comprises a NMOS transistor having a gate coupled to the power supply voltage and a source and drain coupled to the second internal node.

11. A periodic signal generation circuit, comprising:
an oscillator configured to generate a periodic signal toggled based on an amount of charge of an internal node of the oscillator;
a detection signal generation unit configured to detect a toggling period of the periodic signal; and
a reset signal generation unit configured to generate and enable a reset signal in response to a detection signal,
wherein if the periodic signal does not toggle during a predetermined section the oscillator is configured to discharge the internal node,
wherein the reset signal is enabled when a level of the detection signal is higher than a target voltage.

12. The periodic signal generation circuit of claim 11 ,
wherein the oscillator is configured to generate the periodic signal toggled based on the amount of charge of the internal node in response to an enable signal and discharge the internal node in response to the reset signal, and
wherein the detection signal generation unit is configured to detect the toggling period of the periodic signal and generate the detection signal, the detection signal is enabled if the periodic signal is not toggled during the predetermined section.

Assignees

• Sk Hynix Inc

Inventors

• Park Myeong Jae
• Kim Kyung Hoon
• Shin Woo Yeol
• Chi Han Kyu

Classifications

• H03K5/13

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title

• H03K3/0315 Primary

  Ring oscillators · CPC title

• H03K3/014

  Modifications of generator to ensure starting of oscillations · CPC title

• H03K5/19 Primary

  Monitoring patterns of pulse trains (indicating amplitude G01R19/00; indicating frequency G01R23/00; measuring characteristics of individual pulses G01R29/02) · CPC title