Linear FET feedback amplifier

US9722552B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9722552-B2
Application numberUS-201514790096-A
CountryUS
Kind codeB2
Filing dateJul 2, 2015
Priority dateJul 10, 2014
Publication dateAug 1, 2017
Grant dateAug 1, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A circuit that includes a Darlington transistor pair having an input transistor and an output transistor configured to generate an output signal at an output node in response to an input signal received through an input node is disclosed. The circuit has a feedback coupling network coupled between the output node and the input node for feeding back to the input node a portion of an amplified version of the input signal that passes through the input transistor. The circuit further includes a bias feedback network that includes a bias transistor and a resistive network that consists of only resistive elements such that no inductors and no capacitors are provided within the bias feedback network.

First claim

Opening claim text (preview).

What is claimed is: 1. A circuit comprising: a Darlington transistor pair comprising an input transistor and an output transistor wherein a gate of the input transistor is coupled to an input node, a drain of the output transistor is coupled to an output node, and a source of the input transistor is coupled to a gate of the output transistor to generate an output signal at the output node in response to an input signal received through the input node; a feedback coupling network having pair of split feedback resistors coupled between the output node and the input node for feeding back to the input node a portion of an amplified version of the input signal that passes through the input transistor; and a bias feedback network comprising a bias transistor and a resistive network that is coupled between a gate of the bias transistor, the gate of the output transistor, and the source of the input transistor, wherein a drain of the bias transistor is communicatively coupled to the input node through a tap point between the pair of split feedback resistors, and a source of the bias transistor is coupled to a fixed voltage node, and the resistive network consists of only resistive elements such that no inductors and no capacitors are provided between the gate of the bias transistor, the gate of the output transistor, and the source of the input transistor. 2. The circuit of claim 1 wherein the portion of the amplified version of the input signal that passes through the input transistor is phase and amplitude modulated. 3. The circuit of claim 1 wherein the output signal is fed back to the input node via the feedback coupling network. 4. The circuit of claim 1 wherein resistance of the resistive network is sized to attenuate by at least 0.5 dB an RF signal that passes through the resistive network. 5. The circuit of claim 1 wherein resistance of the resistive network is sized to attenuate voltage of an RF signal that passes through the resistive network by a ratio of at least 0.95. 6. The circuit of claim 1 wherein a third-order intercept point (IP3) for the output signal having a frequency of 0.5 GHz improves at least 2.8 dB relative to a bias feedback network having a shunt capacitor. 7. The circuit of claim 1 wherein an IP3 for output power for the output signal having a frequency of 1 GHz improves at least 2.5 dB relative to a bias feedback network having a shunt capacitor. 8. The circuit of claim 1 wherein an IP3 for output power for the output signal having a frequency of 2 GHz improves at least 1.6 dB relative to a bias feedback network having a shunt capacitor. 9. The circuit of claim 1 wherein an IP3 for output power for the output signal having a frequency of 2.7 GHz improves around 1.1 dB relative to a bias feedback network having a shunt capacitor. 10. The circuit of claim 1 wherein an IP3 for output power for the output signal having a frequency of 3 GHz improves around 1.0 dB relative to a bias feedback network having a shunt capacitor. 11. The circuit of claim 1 wherein an IP3 for output power for the output signal having a frequency of 2 GHz and ranging in output power from −30 dB to −10 dB improves at least 1.6 dB relative to a bias feedback network having a shunt capacitor. 12. The circuit of claim 1 wherein an improvement in composite triple beat (CTB) for output power for the output signal approaches 2 dB over a span of cable television (CATV) frequencies that range from 75 MHz to 575 MHz in comparison to bias feedback network with a shunt capacitor. 13. A mobile terminal comprising: an antenna; a duplexer/switch coupled to the antenna; amplifier circuitry selectively coupled to the antenna through the duplexer/switch, the amplifier circuitry comprising: a Darlington transistor pair comprising an input transistor and an output transistor wherein a gate of the input transistor is coupled to an input node, a drain of the output transistor is coupled to an output node, and a source of the input transistor is coupled to a gate of the output transistor to generate an output signal at the output node in response to an input signal received through the input node; a feedback coupling network having pair of split feedback resistors coupled between the output node and the input node for feeding back to the input node a portion of an amplified version of the input signal that passes through the input transistor; and a bias feedback network comprising a bias transistor and a resistive network that is coupled between a gate of the bias transistor, the gate of the output transistor, and the source of the input transistor, wherein a drain of the bias transistor is communicatively coupled to the input node through a tap point between the pair of split feedback resistors, and a source of the bias transistor is coupled to a fixed voltage node, and the resistive network consists of only resistive elements such that no inductors and no capacitors are provided between the gate of the bias transistor, the gate of the output transistor, and the source of the input transistor. 14. The circuit of claim 13 wherein the portion of the amplified version of the input signal that passes through the input transistor is phase and amplitude modulated. 15. The circuit of claim 13 wherein the output signal is fed back to the input node via the feedback coupling network. 16. The circuit of claim 13 wherein resistance of the resistive network is sized to attenuate by at least 0.5 dB an RF signal that passes through the resistive network. 17. The circuit of claim 13 wherein resistance of the resistive network is sized to attenuate voltage of an RF signal that passes through the resistive network by a ratio of at least 0.95. 18. The circuit of claim 13 wherein a third-order intercept point (IP3) for the output signal having a frequency of 0.5 GHz improves at least 2.8 dB relative to a bias feedback network having a shunt capacitor. 19. The circuit of claim 13 wherein an IP3 for output power for the output signal having a frequency of 1 GHz improves around 2.5 dB relative to a bias feedback network having a shunt capacitor. 20. The circuit of claim 13 wherein an IP3 for output power for the output signal having a frequency of 2 GHz improves around 1.6 dB relative to a bias feedback network having a shunt capacitor. 21. The circuit of claim 13 wherein an IP3 for output power for the output signal having a frequency of 2.7 GHz improves around 1.1 dB relative to a bias feedback network having a shunt capacitor. 22. The circuit of claim 13 wherein an IP3 for output power for the output signal having a frequency of 3 GHz improves around 1.0 dB relative to a bias feedback network having a shunt capacitor. 23. The circuit of claim 13 wherein an IP3 for an output power for the output signal having a frequency of 2 GHz and ranging in output power from −30 dB to −10 dB improves around 1.6 dB relative to a bias feedback network having a shunt capacitor. 24. The circuit of claim 13 wherein an improvement in composite triple beat (CTB) for an output power approaches 2 dB over a span of cable television (CATV) frequencies that range from 75 MHz to 575 MHz in comparison to bias feedback network with a shunt capacitor.

Assignees

Inventors

Classifications

  • there being a feedback over the complete amplifier · CPC title

  • H03F3/193Primary

    with field-effect devices (H03F3/195 takes precedence) · CPC title

  • Suppression of signals in the return path, i.e. bidirectional control circuits · CPC title

  • A frequency modulator or demodulator being used in the amplifier circuit · CPC title

  • with field-effect devices (H03F3/347 takes precedence) · CPC title

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What does patent US9722552B2 cover?
A circuit that includes a Darlington transistor pair having an input transistor and an output transistor configured to generate an output signal at an output node in response to an input signal received through an input node is disclosed. The circuit has a feedback coupling network coupled between the output node and the input node for feeding back to the input node a portion of an amplified ve…
Who is the assignee on this patent?
Rf Micro Devices Inc, Qorvo Us Inc
What technology area does this patent fall under?
Primary CPC classification H03F3/193. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).