Memory device

Patent metadata

Field	Value
Publication number	US-9722173-B2
Application number	US-201615248596-A
Country	US
Kind code	B2
Filing date	Aug 26, 2016
Priority date	Mar 20, 2014
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

According to one embodiment, a memory device includes a stacked body and a controller. The stacked body includes a first magnetic layer, a second magnetic layer stacked with the first magnetic layer, and a first nonmagnetic layer provided between the first magnetic layer and the second ferromagnetic layer. The second ferromagnetic layer includes a first portion and a second portion stacked with the first portion. The controller causes a current to flow in the stacked body in a programming period. The programming period includes a first and a second period. The current has a first value in the first period and a second value in the second period. The second value is less than the first value.

First claim

What is claimed is:

1. A memory device, comprising:
a stacked structure including
a first magnetic layer,
a second magnetic layer stacked with the first magnetic layer, the second magnetic layer including
a first portion, and
a second portion stacked with the first portion in a stacking direction of the first magnetic layer and the second magnetic layer,

a magnetic resonance frequency of the first portion being different from a magnetic resonance frequency of the second portion, and
a first nonmagnetic layer provided between the first magnetic layer and the second magnetic layer; and

a controller electrically connected to the stacked structure, the controller causing a current to flow in the stacked structure in a programming period, wherein
the programming period includes a first period and a second period subsequent to and continuous with the first period,
the current has a first value in the first period and a second value in the second period, the second value being less than the first value, and
a length of the first period is not less than 0.9 times and not more than 1.1 times the absolute value of an odd number times of the reciprocal of a magnetic resonance frequency of the second magnetic layer.

2. The memory device according to claim 1 , wherein
the magnetic resonance frequency of the first portion is a first magnetic resonance frequency, and
the magnetic resonance frequency of the second portion is a second magnetic resonance frequency lower than the first magnetic resonance frequency.

3. The memory device according to claim 2 , wherein at least one selected from a group consisting of the first portion and the second portion includes a Heusler alloy including at least one selected from a group consisting of Co, Mn, Fe, Ni, Cu, Rh, Ru, and Pd.

4. The memory device according to claim 2 , wherein at least one selected from a group consisting of the first portion and the second portion includes at least one selected from a group consisting of Co 2 FeSi, Co 2 FeAl, Co 2 FeGa, Co 2 MnGe, Co 2 MnSn, Co 2 MnSi, Co 2 MnGa, Co 2 MnAl, Co 2 MnSb, Co 2 CrGa, Ni 2 MnIn, Ni 2 MnGa, Ni 2 MnSn, Ni 2 MnSb, Ni 2 FeGa, Pd 2 MnSb, Pd 2 MnSn, Cu 2 MnAl, Cu 2 MnSn, Cu 2 MnIn, Rh 2 MnGe, Rh 2 MnPb, Rh 2 MnSn, Pd 2 MnGe, Rh 2 FeSn, Ru 2 FeSn, and Rh 2 FeSb.

5. The memory device according to claim 2 , wherein at least one selected from a group consisting of the first portion and the second portion includes at least one selected from a group consisting of Co 2 HfSn, Co 2 ZrSn, Co 2 HfAl, Co 2 ZrAl, Co 2 HfGa, Co 2 TiSi, Co 2 TiGe, Co 2 TiSn, Co 2 TiGa, Co 2 TiAl, Co 2 VGa, Co 2 VAl, Co 2 TaAl, Co 2 NbGa, Co 2 NbAl, Co 2 VSn, Co 2 NbSn, Co 2 CrAl, Rh 2 NiSn, Rh 2 NiGe, Mn 2 WSn, Fe 2 MnSi, and Fe 2 MnAl.

6. The memory device according to claim 2 , wherein
the first portion includes at least one selected from a group consisting of Co 2 HfSn, Co 2 ZrSn, Co 2 HfAl, Co 2 ZrAl, Co 2 HfGa, Co 2 TiSi, Co 2 TiGe, Co 2 TiSn, Co 2 TiGa, Co 2 TiAl, Co 2 VGa, Co 2 VAl, Co 2 TaAl, Co 2 NbGa, Co 2 NbAl, Co 2 VSn, Co 2 NbSn, Co 2 CrAl, Rh 2 NiSn, Rh 2 NiGe, Mn 2 WSn, Fe 2 MnSi, and Fe 2 MnAl, and
the second portion includes at least one selected from a group consisting of Co 2 FeSi, Co 2 FeAl, Co 2 FeGa, Co 2 MnGe, Co 2 MnSn, Co 2 MnSi, Co 2 MnGa, Co 2 MnAl, Co 2 MnSb, Co 2 CrGa, Ni 2 MnIn, Ni 2 MnGa, Ni 2 MnSn, Ni 2 MnSb, Ni 2 FeGa, Pd 2 MnSb, Pd 2 MnSn, Cu 2 MnAl, Cu 2 MnSn, Cu 2 MnIn, Rh 2 MnGe, Rh 2 MnPb, Rh 2 MnSn, Pd 2 MnGe, Rh 2 FeSn, Ru 2 FeSn, and Rh 2 FeSb.

7. The memory device according to claim 2 , wherein
the first magnetic resonance frequency is 20 GHz or more, and
the second magnetic resonance frequency is less than 20 GHz.

8. The memory device according to claim 1 , wherein
a perpendicular magnetization component parallel to the stacking direction of a magnetization of the first magnetic layer is larger than an in-plane magnetization component perpendicular to the stacking direction of the magnetization of the first magnetic layer,
the perpendicular magnetization component of a magnetization of the first portion is larger than the in-plane magnetization component of the magnetization of the first portion, and
the perpendicular magnetization component of a magnetization of the second portion is larger than the in-plane magnetization component of the magnetization of the second portion.

9. The memory device according to claim 1 , wherein
a plurality of the second magnetic layers and a plurality of the first nonmagnetic layers are provided,
the plurality of second magnetic layers is arranged in an in-plane direction perpendicular to the stacking direction, and
the plurality of first nonmagnetic layers is disposed respectively between the first magnetic layer and each of the plurality of second magnetic layers.

10. The memory device according to claim 1 , wherein
a plurality of the second magnetic layers is provided,
the plurality of second magnetic layers is arranged in an in-plane direction perpendicular to the stacking direction, and
the first nonmagnetic layer is disposed between the first magnetic layer and the plurality of second magnetic layers.

11. The memory device according to claim 1 , further comprising:
a first interconnect electrically connected to the first magnetic layer; and
a second interconnect electrically connected to the second magnetic layer,
the controller being connected to the stacked structure via the first interconnect and the second interconnect.

12. The memory device according to claim 11 , further comprising a selection transistor provided between the first magnetic layer and the first interconnect and/or between the second magnetic layer and the second interconnect.

13. The memory device according to claim 1 , wherein a length of the second magnetic layer in a direction perpendicular to the stacking direction is 35 nanometers or less.

14. The memory device according to claim 1 , further comprising a magnetic shield opposing at least a portion of a side surface of the stacked structure extending in the stacking direction.

15. The memory device according to claim 1 , wherein a length of the stacked structure in a direction perpendicular to the stacking direction decreases in a direction from the first magnetic layer toward the second magnetic layer.

16. The memory device according to claim 1 , wherein the programming period is not less than 10 nanoseconds and not more than 30 nanoseconds.

17. The memory device according to claim 1 , wherein the first period is 2 nanoseconds or less.

18. The memory device according to claim 1 , wherein the second value is not more than 0.8 times the first value.

19. The memory device according to claim 1 , wherein a time for the current to change from the second value to the first value is less than 300 picoseconds.

20. The memory device according to claim 1 , wherein
a direction of a magnetization of the first magnetic layer is fixed,
a direction of a magnetization of the first portion is changeable,
a direction of a magnetization of the second portion is changeable, and
the direction of the magnetization of the first portion and the direction of the magnetization of the second portion are oriented in a direction corresponding to an orientation of the current.

21. A memory device, comprising:
a stacked structure including
a first magnetic layer,
a second magnetic layer stacked with the first magnetic layer, the second magnetic layer including
a first portion, and
a second portion stacked with the

Assignees

• Toshiba Kk

Inventors

• Saida Daisuke
• Shimomura Naoharu

Classifications

• G11C11/165

  Auxiliary circuits · CPC title

• H01L43/08

  Electricity · mapped topic

• G11C11/1693

  Timing circuits or methods · CPC title

• H01L43/10 Primary

  Electricity · mapped topic

• G11C11/1675

  Writing or programming circuits or methods · CPC title