Bandgap grading of CZTS solar cell

Patent metadata

Field	Value
Publication number	US-9722120-B2
Application number	US-201514853463-A
Country	US
Kind code	B2
Filing date	Sep 14, 2015
Priority date	Sep 14, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A method for fabricating a photovoltaic device includes forming a polycrystalline absorber layer including Cu—Zn—Sn—S(Se) (CZTSSe) over a substrate. The absorber layer is rapid thermal annealed in a sealed chamber having elemental sulfur within the chamber. A sulfur content profile is graded in the absorber layer in accordance with a size of the elemental sulfur and an anneal temperature to provide a graduated bandgap profile for the absorber layer. Additional layers are formed on the absorber layer to complete the photovoltaic device.

First claim

The invention claimed is:

1. A method for fabricating a photovoltaic device, comprising:
forming a polycrystalline absorber layer including Cu—Zn—Sn—S(Se) (CZTSSe) over a substrate, wherein the absorber layer has a front surface;
rapid thermal annealing the absorber layer in a sealed chamber having a piece of elemental sulfur within the chamber, wherein the elemental sulfur is located other than on the front surface of the absorber layer;
grading a sulfur content profile in the absorber layer in accordance with a shape and dimensions of the piece of elemental sulfur and an anneal temperature to provide a graduated bandgap profile for the absorber layer; and
forming additional layers on the absorber layer to complete the photovoltaic device.

2. The method as recited in claim 1 , wherein rapid thermal annealing includes applying a temperature of about 590 degrees C. for about 120 seconds to concurrently increase grain size of grains in the absorber layer.

3. The method as recited in claim 1 , wherein rapid thermal annealing includes applying a temperature of between about 290 degrees C. and about 490 degrees C. for about 120 seconds.

4. The method as recited in claim 1 , wherein rapid thermal annealing includes increasing grain size for the CZTSSe in the absorber layer.

5. The method as recited in claim 1 , wherein grading the sulfur content profile includes higher sulfur content at a junction with the additional layers.

6. The method as recited in claim 1 , wherein grading the sulfur content profile includes higher sulfur content at the front surface and a back surface of the absorber layer.

7. The method as recited in claim 1 , further comprising controlling secondary phase formation of sulfur compounds in the chamber.

8. The method as recited in claim 7 , wherein controlling secondary phase formation of sulfur compounds in the chamber includes placing a piece of SnS in the chamber.

9. The method as recited in claim 1 , wherein forming additional layers on the absorber layer includes:
forming a semiconductor layer on the absorber layer; and
forming a transparent conductor over the semiconductor layer.

10. A method for fabricating a photovoltaic device, comprising:
forming a polycrystalline absorber layer including Cu—Zn—Sn—S(Se) (CZTSSe) over a substrate, wherein the absorber layer has a front surface;
placing a piece of elemental sulfur in a chamber, wherein the elemental sulfur is located other than on the front surface of the absorber layer;
placing a secondary phase blocker in the chamber;
rapid thermal annealing the absorber layer with the elemental sulfur and the secondary phase blocker in the chamber after being sealed by applying a temperature of between about 290 degrees C. and about 490 degrees C. for about 120 seconds;
grading a sulfur content profile in the absorber layer in accordance with a shape and dimensions of the piece of elemental sulfur and an anneal temperature to provide a graduated bandgap profile for the absorber layer; and
forming additional layers on the absorber layer to complete the photovoltaic device.

11. The method as recited in claim 10 , wherein grading the sulfur content profile includes higher sulfur content at a junction with the additional layers.

12. The method as recited in claim 10 , wherein grading the sulfur content profile includes higher sulfur content at the front surface and a back surface of the absorber layer.

13. The method as recited in claim 10 , wherein placing the secondary phase blocker includes placing a piece of SnS in the chamber.

14. The method as recited in claim 10 , wherein forming additional layers on the absorber layer includes:
forming a semiconductor layer on the absorber layer; and
forming a transparent conductor over the semiconductor layer.

Assignees

• IBM

Inventors

• Gershon Talia S
• Hopstaken Marinus J P
• Kim Jeehwan
• Lee Yun Seog

Classifications

• H01L31/0326

  Electricity · mapped topic

• H01L31/065 Primary

  Electricity · mapped topic

• H01L31/1864

  Electricity · mapped topic

• H01L31/0368

  Electricity · mapped topic

• H10F77/244

  made of transparent conductive layers, e.g. transparent conductive oxide [TCO] layers · CPC title