Semiconductor device

Patent metadata

Field	Value
Publication number	US-9722075-B2
Application number	US-201415106918-A
Country	US
Kind code	B2
Filing date	Oct 16, 2014
Priority date	Dec 25, 2013
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

Described herein is a semiconductor device including a semiconductor substrate in which an element region and a termination region surrounding the element region are provided. The element region includes: a gate trench; a gate insulating film; and a gate electrode. The termination region includes: a plurality of termination trenches provided around the element region; an inner trench insulating layer located inside of each of the plurality of termination trenches; and an upper surface insulating layer located at an upper surface of the semiconductor substrate in the termination region. The upper surface insulating layer includes a first portion and a second portion having a thinner thickness than the first portion and located at a location separated from the element region than the first portion, and a gate wiring is located at an upper surface of the first portion and is not located at an upper surface of the second portion.

First claim

The invention claimed is:

1. A semiconductor device comprising a semiconductor substrate in which an element region and a termination region surrounding the element region are provided,
wherein
the element region comprises:
a gate trench;
a gate insulating film covering an inner surface of the gate trench; and
a gate electrode located inside of the gate insulating film,
the termination region comprises:
a plurality of termination trenches provided around the element region;
an inner trench insulating layer located inside of each of the plurality of termination trenches; and
an upper surface insulating layer located at an upper surface of the semiconductor substrate in the termination region,
the upper surface insulating layer comprises a first portion and a second portion having a thinner thickness than the first portion and located at a location separated from the element region than the first portion, and
a gate wiring is located at an upper surface of the first portion and is not located at an upper surface of the second portion.

2. The semiconductor device as in claim 1 , wherein
the upper surface insulating layer comprises:
a first layer; and
a second layer having higher phosphorus and boron contents per unit volume than the first layer and located at an upper surface of the first layer,
the upper surface insulating layer in a first region comprises the first layer and the second layer,
the upper surface insulating layer in a second region which is a location separated from the element region than the first region, comprises the second layer and the first layer having a thinner thickness than the first layer in the first region, or comprises the second layer and does not comprise the first layer, and
the gate wiring is located at an upper surface of the upper insulating layer in the first region and is not located at an upper surface of the upper insulating layer in the second region.

3. A semiconductor device comprising a semiconductor substrate in which an element region and a termination region surrounding the element region are provided,
wherein
the element region comprises:
a gate trench;
a gate insulating film covering an inner surface of the gate trench; and
a gate electrode located inside of the gate insulating film,
the termination region comprises:
a plurality of termination trenches provided around the element region; and
an insulating layer provided inside of each of the plurality of termination trenches and at an upper surface of the semiconductor substrate,
the insulating layer comprises:
a first layer; and
a second layer having higher phosphorus and boron contents per unit volume than the first layer and located at an upper surface of the first layer,
a plurality of concave portions is provided at an upper surface of the first layer,
each of the concave portions is extended along a partition wall between adjacent ones of the termination trenches,
an interval between adjacent ones of the concave portions is longer than an interval between the adjacent ones of the termination trenches,
the second layer is filled in each of the concave portions, and
a gate wiring is located at an upper surface of the insulating layer.

4. The semiconductor device as in claim 3 , wherein
the first layer comprises:
a first insulating layer covering an inner surface of each of the plurality of termination trenches; and
a second insulating layer filled inside of the plurality of termination trenches covered by the first insulating layer, and
a refraction index of the first insulating layer is larger than a refraction index of the second insulating layer.

5. The semiconductor device as in claim 4 , wherein
the first insulating layer and the second layer are laminated on the partition wall corresponding to each of the concave portions, the second insulating layer is not laminated on the partition wall corresponding to each of the concave portions, and
the first insulating layer, the second insulating layer, and the second layer are laminated on the partition wall not corresponding to the concave portions.

6. The semiconductor device as in claim 5 , wherein
the first layer comprises a third insulating layer provided at an upper surface of the second insulating layer, and
a refraction index of the third insulating layer is larger than the refraction index of the second insulating layer.

Assignees

• Soeno Akitaka
• Fukuoka Yuji
• Toyota Motor Co Ltd

Inventors

• Soeno Akitaka
• Fukuoka Yuji

Classifications

• H01L29/7397

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic

• H01L29/0634

  Electricity · mapped topic

• H01L29/0661

  Electricity · mapped topic

• H01L29/78

  Electricity · mapped topic