Pad electrode structure, flat display apparatus comprising the pad electrode structure, and the method of manufacturing the flat display apparatus

Patent metadata

Field	Value
Publication number	US-9722009-B2
Application number	US-201514681034-A
Country	US
Kind code	B2
Filing date	Apr 7, 2015
Priority date	Oct 13, 2014
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A pad electrode structure including a substrate, an insulating layer on the substrate, a pad electrode on a portion of the insulating layer, and an organic insulating layer on the pad electrode and having an opening exposing an upper surface of the pad electrode, wherein an insertion area is in the insulating layer near the substrate, and wherein the organic insulating layer is separated from an end portion of the substrate, and a portion of the organic insulating layer is in the insertion area.

First claim

What is claimed is:

1. A pad electrode structure comprising:
a substrate;
an insulating layer on the substrate;
a pad electrode on a portion of the insulating layer; and
an organic insulating layer on the pad electrode and having an opening exposing an upper surface of the pad electrode,
wherein an insertion area is in the insulating layer and filled with the organic insulating layer,
wherein the organic insulating layer in the insertion area is contacted with the substrate, and
wherein the organic insulating layer is separated from an end portion of the substrate.

2. The pad electrode structure of claim 1 , wherein the organic insulating layer comprises a first area on the pad electrode, a second area on the insulating layer, and a third area in the insertion area.

3. The pad electrode structure of claim 2 , wherein a minimum height of the third area with respect to an upper surface of the insulating layer is greater than 0 and is smaller than a minimum height of the second area with respect to an upper surface of the insulating layer.

4. The pad electrode structure of claim 2 , wherein a slope of a top of the third area with respect to an upper surface of the insulating layer is greater than a gradient slope of a top of the second area with respect to an upper surface of the insulating layer.

5. The pad electrode structure of claim 1 , wherein a depth of the insertion area is less than or equal to a thickness of the insulating layer.

6. The pad electrode structure of claim 1 , wherein the insulating layer comprises an inorganic insulating material different from a material of the organic insulating layer.

7. The pad electrode structure of claim 1 , further comprising:
a main conductive bonding layer filling the opening of the organic insulating layer; and
a dummy conductive bonding layer contacting the organic insulating layer and the insulating layer.

8. The pad electrode structure of claim 7 , further comprising a printed circuit board contacting the main conductive bonding layer.

9. A flat display apparatus comprising:
a plurality of pixels; and
a pad electrode structure electrically connected to the plurality of pixels,
wherein the pad electrode structure comprises:
a substrate;
an insulating layer on the substrate;
a pad electrode on a portion of the insulating layer; and
an organic insulating layer on the pad electrode and having an opening exposing an upper surface of the pad electrode,
wherein an insertion area is in the insulating layer and filled with the organic insulating layer, wherein the organic insulating layer in the insertion area is contacted with the substrate, and wherein the organic insulating layer is separated from an end portion of the substrate.

10. The flat display apparatus of claim 9 , wherein the organic insulating layer comprises a first area on the pad electrode, a second area on the insulating layer, and a third area in the insertion area.

11. The flat display apparatus of claim 10 , wherein a minimum height of the third area with respect to an upper surface of the insulating layer is greater than 0 and is less than a minimum height of the second area with respect to an upper surface of the insulating layer.

12. The flat display apparatus of claim 10 , wherein a slope of a top of the third area with respect to an upper surface of the insulating layer is greater than a slope of a top of the second area with respect to an upper surface of the insulating layer.

13. The flat display apparatus of claim 9 , wherein a depth of the insertion area is less than or equal to a thickness of the insulating layer.

14. The flat display apparatus of claim 9 , wherein the insulating layer comprises an inorganic insulating material different from a material of the organic insulating layer.

15. The flat display apparatus of claim 9 , further comprising:
a main conductive bonding layer filling the opening of the organic insulating layer; and
a dummy conductive bonding layer contacting the organic insulating layer and the insulating layer.

16. The flat display apparatus of claim 15 , further comprising a printed circuit board contacting the main conductive bonding layer.

17. A method of manufacturing a flat display apparatus, the method comprising:
forming an insulating layer on a substrate;
forming an insertion area in the insulating layer, the insertion area being formed toward the substrate, and forming a pad electrode on the insulating layer; and
forming an organic insulating layer to expose a portion of the pad electrode and a portion of the insulating layer,
wherein, in the forming of the organic insulating layer, at least a portion of the organic insulating layer fills the insertion area, and
wherein the organic insulating layer in the insertion area is contacted with the substrate.

18. The method of claim 17 , further comprising spreading a conductive bonding material on the opening and arranging a printed circuit board (PCB) to contact the conductive bonding material,
wherein, in the arranging of the PCB, the conductive bonding material is pressed by the PCB, thereby forming a main conductive bonding layer in the opening, and a dummy conductive bonding layer, the dummy conductive bonding layer contacting the insulating layer and the organic insulating layer.

Assignees

• Samsung Display Co Ltd

Inventors

• Chae Jongwon

Classifications

• H10K71/851

  Division of substrate · CPC title

• H10K59/124

  Insulating layers formed between TFT elements and OLED elements · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H01L27/3297

  Electricity · mapped topic

• H01L27/3276 Primary

  Electricity · mapped topic