Display device and electronic device including the same

Patent metadata

Field	Value
Publication number	US-9721971-B2
Application number	US-201414507204-A
Country	US
Kind code	B2
Filing date	Oct 6, 2014
Priority date	Dec 4, 2009
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

One embodiment of the present invention provides a highly reliably display device in which a high mobility is achieved in an oxide semiconductor. A first oxide component is formed over a base component. Crystal growth proceeds from a surface toward an inside of the first oxide component by a first heat treatment, so that a first oxide crystal component is formed in contact with at least part of the base component. A second oxide component is formed over the first oxide crystal component. Crystal growth is performed by a second heat treatment using the first oxide crystal component as a seed, so that a second oxide crystal component is formed. Thus, a stacked oxide material is formed. A transistor with a high mobility is formed using the stacked oxide material and a driver circuit is formed using the transistor.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a substrate comprising a top surface;
a gate electrode layer over the substrate, and comprising a top surface and a side surface, the side surface having an inclination with respect to the top surface of the substrate;
an oxide semiconductor layer over the substrate with the gate electrode layer interposed therebetween, and comprising a first portion facing the top surface of the gate electrode layer, and a second portion inclined in response to the inclination of the side surface of the gate electrode layer;
a gate insulating layer between the gate electrode layer and the oxide semiconductor layer;
a source electrode layer and a drain electrode layer over and in electrical contact with the oxide semiconductor layer,
wherein the oxide semiconductor layer has crystallinity, and
wherein c-axis of crystals of the oxide semiconductor layer are substantially perpendicular to a surface of the oxide semiconductor layer in both the first portion and the second portion.

2. A semiconductor device comprising:
a substrate comprising a top surface;
a gate electrode layer over the substrate, and comprising a top surface and a side surface, the side surface having an inclination with respect to the top surface of the substrate;
an oxide semiconductor layer over the substrate with the gate electrode layer interposed therebetween, and comprising a first portion facing the top surface of the gate electrode layer, and a second portion inclined in response to the inclination of the side surface of the gate electrode layer;
a gate insulating layer between the gate electrode layer and the oxide semiconductor layer, the gate insulating layer comprising a first stack of a first silicon nitride layer and a first silicon oxide layer;
a source electrode layer and a drain electrode layer on and in direct contact with the oxide semiconductor layer;
an insulating layer comprising a second stack of a second silicon oxide layer and a second nitride layer over the second silicon oxide layer, the second silicon oxide layer being in direct contact with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer,
wherein the oxide semiconductor layer has crystallinity, and
wherein c-axis of crystals of the oxide semiconductor layer are substantially perpendicular to a surface of the oxide semiconductor layer in both the first portion and the second portion.

3. A semiconductor device comprising:
a substrate comprising a top surface;
a gate electrode layer over the substrate, and comprising a top surface and a side surface, the side surface having an inclination with respect to the top surface of the substrate;
an oxide semiconductor layer over the substrate with the gate electrode layer interposed therebetween, and comprising a first portion facing the top surface of the gate electrode layer, and a second portion inclined in response to the inclination of the side surface of the gate electrode layer;
a gate insulating layer between the gate electrode layer and the oxide semiconductor layer;
a source electrode layer and a drain electrode layer over and in electrical contact with the oxide semiconductor layer,
wherein the source electrode layer and the drain electrode layer overlap with the gate electrode layer and are on and in direct contact with side end portions of the oxide semiconductor layer,
wherein the oxide semiconductor layer has crystallinity, and
wherein c-axis of crystals of the oxide semiconductor layer are substantially perpendicular to a surface of the oxide semiconductor layer in both the first portion and the second portion.

4. The semiconductor device according to claim 1 , further comprising:
an oxide layer on and in direct contact with the oxide semiconductor layer.

5. The semiconductor device according to claim 3 , further comprising:
an oxide layer on and in direct contact with the oxide semiconductor layer.

6. The semiconductor device according to claim 1 , further comprising:
a silicon oxide layer on and in direct contact with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer; and
a silicon nitride layer over the silicon oxide layer.

7. The semiconductor device according to claim 3 , further comprising:
a silicon oxide layer on and in direct contact with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer; and
a silicon nitride layer over the silicon oxide layer.

8. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor layer is sandwiched between insulating layers each comprising silicon, nitrogen, and oxygen.

9. The semiconductor device according to claim 3 ,
wherein the oxide semiconductor layer is sandwiched between insulating layers each comprising silicon, nitrogen, and oxygen.

10. The semiconductor device according to claim 2 ,
wherein the source electrode layer and the drain electrode layer overlap with the gate electrode layer and are on and in direct contact with side end portions of the oxide semiconductor layer.

11. The semiconductor device according to claim 1 , further comprising:
an inorganic insulating layer over the source electrode layer and the drain electrode layer;
an organic insulating layer over the inorganic insulating layer;
a conductive layer over the organic insulating layer and electrically connected to one of the source electrode layer and the drain electrode layer via a contact hole in the organic insulating layer.

12. The semiconductor device according to claim 2 , further comprising:
an organic insulating layer over the second silicon nitride layer;
a conductive layer over the organic insulating layer and electrically connected to one of the source electrode layer and the drain electrode layer via a contact hole in the organic insulating layer.

13. The semiconductor device according to claim 3 , further comprising:
an inorganic insulating layer over the source electrode layer and the drain electrode layer;
an organic insulating layer over the inorganic insulating layer;
a conductive layer over the organic insulating layer and electrically connected to one of the source electrode layer and the drain electrode layer via a contact hole in the organic insulating layer.

14. The semiconductor device according to claim 11 ,
wherein the conductive layer is a pixel electrode.

15. The semiconductor device according to claim 12 ,
wherein the conductive layer is a pixel electrode.

16. The semiconductor device according to claim 13 ,
wherein the conductive layer is a pixel electrode.

17. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

18. The semiconductor device according to claim 2 ,
wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

19. The semiconductor device according to claim 3 ,
wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

Assignees

• Semiconductor Energy Lab

Inventors

• Koyama Jun
• Yamazaki Shunpei

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/13454

  Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence) · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G02F1/133345

  Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence) · CPC title