Apparatus and methods for multi-die packaging

Patent metadata

Field	Value
Publication number	US-9721881-B1
Application number	US-201615142644-A
Country	US
Kind code	B1
Filing date	Apr 29, 2016
Priority date	Apr 29, 2016
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A method of forming a semiconductor device assembly includes forming an interposer having an opening extending from a first major surface to a second major surface of the interposer and a plurality of external connectors on the second major surface. The method further includes attaching the first major surface of the interposer to a packaged semiconductor device, wherein the opening of the interposer exposes the packaged semiconductor device.

First claim

What is claimed is:

1. A method of forming a semiconductor device assembly, comprising:
forming an interposer having an opening extending from a first major surface to a second major surface of the interposer and a plurality of external connectors on the second major surface, wherein the external connectors are directly attached to conductive vias that extend from the first major surface to the second major surface of the interposer; and
after forming the interposer with the external connectors, attaching the first major surface of the interposer to a packaged semiconductor device, wherein the opening of the interposer exposes the packaged semiconductor device.

2. The method of claim 1 , wherein the plurality of external connector has a pitch in a range of 0.4 to 1.3 mm.

3. The method of claim 1 , wherein the plurality of external connectors comprises one of solder balls, solder bumps, or landing pads.

4. The method of claim 1 , wherein the attaching the first major surface of the interposer to the packaged semiconductor device is performed with a second plurality of external connectors.

5. The method of claim 1 , wherein the interposer and first plurality of external connectors is formed using ball grid array (BGA) technology or flip chip technology.

6. The method of claim 1 , further comprising:
after the attaching the first major surface of the interposer to the packaged semiconductor device, attaching the first plurality of external connectors to a printed circuit board (PCB), wherein the interposer is between the packaged semiconductor device and the PCB.

7. The method of claim 6 , further comprising:
prior to attaching the first plurality of solder balls to the PCB, attaching a set of components to the PCB, wherein, after the attaching the first plurality of external connectors to the PCB, the opening surrounds the set of components.

8. The method of claim 7 , wherein the set of components comprises a second packaged semiconductor device.

9. The method of claim 7 , wherein the set of components comprises a passive device.

10. The method of claim 7 , wherein the opening completely surrounds the set of components.

11. The method of claim 1 , wherein the packaged semiconductor device comprises a plurality of semiconductor die.

12. The method of claim 1 , wherein the interposer and the plurality of external connectors together has a thickness in a range of 0.1 mm to 1 mm.

13. A method of forming a semiconductor device assembly, comprising:
attaching an interposer to a package substrate of a first packaged semiconductor device having a first die, wherein the interposer includes an opening and a plurality of solder balls attached to conductive vias that extend from a first major surface of the interposer to a second major surface of the interposer prior to the attaching the interposer to the first packaged semiconductor device, and wherein the interposer is attached such that the opening surrounds the first die; and
attaching a second packaged semiconductor device to the second major surface of the interposer.

14. The method of claim 13 , wherein the first die is attached to a first major surface of the package substrate and the attaching the interposer to the package substrate comprises attaching each solder ball of the plurality of solder balls to a bond pad on the first major surface of the package substrate.

15. The method of claim 13 , wherein the attaching the second packaged semiconductor die to the second major surface of the interposer comprises attaching the second package semiconductor die to the second major surface of the interposer using a second plurality of solder balls.

16. A method of making a semiconductor device assembly comprising:
attaching a first major surface of an interposer to a packaged semiconductor device, wherein the interposer has an opening extending from the first major surface to a second major surface of the interposer and a plurality of external connectors on the second major surface prior to the attaching, the external connectors are in direct contact with conductive vias in the interposer that extend from the first major surface to the second manor surface, and wherein the opening of the interposer exposes the packaged semiconductor device.

17. The method of claim 16 , further comprising:
attaching a second plurality of external connectors between the packaged semiconductor substrate and the first major surface of the interposer.

18. The method of claim 17 , wherein the plurality of external connectors has a pitch in a range of 0.2 mm to 1.3 mm.

19. The method of claim 18 , further comprising:
attaching the plurality of solder balls to a PCB, wherein the interposer is between the packaged semiconductor device and the PCB.

20. The method of claim 19 , further comprising:
attaching a set of components to the PCB, wherein the opening surrounds the set of components.

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Gong Zhiwei
• Gao Wei

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title

• H10W72/50

  Bond wires · CPC title