High performance isolated vertical bipolar junction transistor and method for forming in a CMOS integrated circuit

Patent metadata

Field	Value
Publication number	US-9721849-B2
Application number	US-201615255341-A
Country	US
Kind code	B2
Filing date	Sep 2, 2016
Priority date	Dec 28, 2012
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types.

First claim

What is claimed is:

1. A method of forming an integrated circuit, comprising the steps of:
providing a substrate comprising a p-type semiconductor material, said substrate including an area for an NMOS transistor, an area for a PMOS transistor, an area for an isolated n-channel DEMOS transistor, and an area for an isolated vertical PNP transistor;
concurrently forming a first shallow n-type well surrounding said isolated n-channel DEMOS transistor, a second shallow n-type well surrounding said isolated vertical PNP transistor, and third shallow n-type well providing a body region for said PMOS transistor of said integrated circuit;
concurrently forming a first deep n-type well underlying said isolated n-channel DEMOS transistor and a second deep n-type well underlying said isolated vertical PNP transistor, so that said first shallow n-type well connects with said first deep n-type well so as to isolate said isolated n-channel DEMOS transistor from said p-type semiconductor material of said substrate, and said second shallow n-type well connects with said second deep n-type well so as to isolate said isolated vertical PNP transistor from said p-type semiconductor material of said substrate;
concurrently forming a first upper n-type layer providing an extended drain of said isolated n-channel DEMOS transistor and a second upper n-type layer providing a base of said isolated vertical PNP transistor; and
concurrently forming a first lower p-type layer below said first upper n-type layer and a second lower p-type layer below said second upper n-type layer, said second lower p-type layer providing a collector of said isolated vertical PNP transistor.

2. The method of claim 1 , further comprising concurrently forming:
a first shallow p-type well providing a body region for said isolated n-channel DEMOS transistor;
a second shallow p-type well providing connection to said collector of said isolated vertical PNP transistor; and
a third shallow p-type well providing a body region for said NMOS transistor.

3. The method of claim 1 , further comprising concurrently forming:
a first p-type diffused region which provides a body contact region of said isolated n-channel DEMOS transistor;
a second p-type diffused region which provides an emitter of said isolated vertical PNP transistor;
a third p-type diffused region which provides a collector contact region of said isolated vertical PNP transistor; and
a pair of fourth p-type diffused regions which provides source and drain regions of said PMOS transistor.

4. The method of claim 1 , further comprising the steps:
concurrently forming:
a first silicide block portion of a silicide block layer is disposed on said isolated n-channel DEMOS transistor between a drain contact region of said isolated n-channel DEMOS transistor and a gate structure of said isolated n-channel DEMOS transistor; and
a second silicide block portion of said silicide block layer is disposed on said isolated vertical PNP transistor between an emitter of said isolated vertical PNP transistor and a base contact region of said isolated vertical PNP transistor; and

forming metal silicide on exposed areas of semiconductor material at a top surface of said substrate, such that:
said first silicide block portion blocks said metal silicide between said drain contact region of said isolated n-channel DEMOS transistor and said gate structure of said isolated n-channel DEMOS transistor; and
second silicide block portion blocks said metal silicide between said emitter of said isolated vertical PNP transistor and said base contact region of said isolated vertical PNP transistor.

5. The method of claim 1 , further comprising the steps:
concurrently forming:
a first gate structure of said NMOS transistor;
a second gate structure of said PMOS transistor;
a third gate structure of said isolated n-channel DEMOS transistor; and
a fourth gate structure of said isolated vertical PNP transistor, such that said fourth gate structure is disposed between an emitter of said isolated vertical PNP transistor and a base contact region of said isolated vertical PNP transistor; and

forming metal silicide on exposed areas of semiconductor material at a top surface of said substrate, such that fourth gate structure blocks said metal silicide between said emitter of said isolated vertical PNP transistor and said base contact region of said isolated vertical PNP transistor.

6. The method of claim 5 , further comprising concurrently implanting n-type dopants through said first gate structure of said NMOS transistor and through said fourth gate structure of said isolated vertical PNP transistor.

7. The method of claim 5 , further comprising concurrently implanting n-type dopants through said third gate structure of said isolated n-channel DEMOS transistor and through said fourth gate structure of said isolated vertical PNP transistor.

8. The method of claim 1 , in which said second shallow n-type well is formed so as to extend under an element of field oxide and contact said second upper n-type layer providing said base of said isolated vertical PNP transistor.

9. The method of claim 1 , in which said second upper n-type layer providing said base of said isolated vertical PNP transistor is formed so as to extend under an element of field oxide and contact said second shallow n-type well.

10. The method of claim 1 , further comprising concurrently forming:
a first shallow p-type well in said substrate, said first shallow p-type well providing a body region for said isolated n-channel DEMOS transistor;
a second shallow p-type well in said substrate, said second shallow p-type well providing connection to said collector of said isolated vertical PNP transistor; and
a third shallow p-type well in said substrate, said third shallow p-type well providing a body region for said NMOS transistor.

11. The method of claim 1 , further comprising concurrently implanting p-type dopants into drain extension regions of said PMOS transistor and into an emitter region of said isolated vertical PNP transistor.

Assignees

• Texas Instruments Inc

Inventors

• Robinson Derek W
• Chatterjee Amitava

Classifications

• H10W10/0143

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L21/76229

  Electricity · mapped topic