Data protection method, memory control circuit unit and memory storage apparatus

Patent metadata

Field	Value
Publication number	US-9721669-B2
Application number	US-201514887332-A
Country	US
Kind code	B2
Filing date	Oct 20, 2015
Priority date	Aug 19, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A data protection method for a memory storage apparatus is provided. The method includes obtaining a current system time from a host system as a boot time, if the memory storage apparatus is powered on, and a basic input/output system of the host system loads and executes instruction programs in the expansion ROM of the memory storage apparatus for transmitting the current system time to the memory storage apparatus. The method also includes obtaining a shutdown time corresponding to the memory storage apparatus; calculating an off time from the shutdown time to the boot time and performing a refresh operation on physical erasing units of a rewritable non-volatile memory in the memory storage apparatus if the off time is longer than an off time threshold.

First claim

What is claimed is:

1. A data protection method, for a memory storage apparatus comprising a rewritable non-volatile memory module having a plurality of physical erasing units, the data protection method comprising:
obtaining a current system time from a host system as a boot time if the memory storage apparatus is powered on, wherein a basic input/output system of the host system loads and executes instruction programs in an expansion ROM of the memory storage apparatus for transmitting the current system time to the memory storage apparatus;
obtaining a shutdown time corresponding to the memory storage apparatus;
calculating an off time from the shutdown time to the boot time; and
performing a refresh operation on physical erasing units if the off time is longer than an off time threshold.

2. The data protection method as recited in claim 1 , further comprising:
obtaining a total off time previously recorded and calculating a sum of the off time and the total off time if the off time is not longer than the off time threshold;
performing the refresh operation on the physical erasing units if the sum of the off time and the total off time is longer than the off time threshold; and
resetting the total off time after performing the refresh operation on the physical erasing units.

3. The data protection method as recited in claim 2 , further comprising:
updating the total off time via the sum of the off time and the total off time if the sum of the off time and the total off time is not longer than the off time threshold, and storing the updated total off time in at least one of the physical erasing units.

4. The data protection method as recited in claim 1 , further comprising:
continuing to record a refresh operation interval time after performing the refresh operation on the physical erasing units; and
performing the refresh operation on physical erasing units if the refresh operation interval time is longer than an interval time threshold.

5. The data protection method as recited in claim 1 , wherein the step of performing the refresh operation on physical erasing units comprise:
checking and calculating a number of error bits of valid data stored in a first physical erasing unit among the physical erasing units;
copying the valid data of the first physical erasing unit into a second physical erasing unit of the physical erasing units if the number of error bits of the valid data of the first physical erasing unit is greater than a predetermined error bit number threshold; and
non-copying the valid data of the first physical erasing unit into the second physical erasing unit of the physical erasing units if the number of error bits of the valid data of the first physical erasing unit is not greater than the predetermined error bit number threshold.

6. The data protection method as recited in claim 5 , wherein the physical erasing units belong to a system area of the rewritable non-volatile memory module.

7. The data protection method as recited in claim 1 , further comprising:
recording the shutdown time in one of the physical erasing units of the rewritable non-volatile memory module, wherein the shutdown time is recorded before the memory storage apparatus is powered off.

8. The data protection method as recited in claim 7 , wherein the step of obtaining the shutdown time corresponding to the memory storage apparatus comprise:
reading the shutdown time from the one of the physical erasing units of the rewritable non-volatile memory module if the memory storage apparatus is powered on.

9. A memory control circuit unit, disposed in a memory storage apparatus, for controlling a rewritable non-volatile memory module of the memory storage apparatus, wherein the rewritable non-volatile memory module comprises a plurality of physical erasing units, the memory control circuit unit comprising:
a host interface configured to couple to a host system;
a memory interface configured to couple to the rewritable non-volatile memory module; and
a memory management circuit coupled to the host interface and the memory interface,
wherein the memory management circuit is configured to obtain a current system time from the host system as a boot time if the memory storage apparatus is powered on, wherein a basic input/output system of the host system loads and executes instruction programs in an expansion ROM of the memory storage apparatus for transmitting the current system time to the memory storage apparatus,
wherein the memory management circuit is further configured to obtain a shutdown time corresponding to the memory storage apparatus,
wherein the memory management circuit is further configured to calculate an off time from the shutdown time to the boot time,
wherein the memory management circuit is further configured to perform a refresh operation on the physical erasing units if the off time is longer than an off time threshold.

10. The memory control circuit unit as recited in claim 9 , wherein the memory management circuit is further configured to obtain a total off time previously recorded and to calculate a sum of the off time and the total off time if the off time is not longer than the off time threshold,
wherein the memory management circuit is further configured to perform the refresh operation on the physical erasing units if the sum of the off time and the total off time is longer than the off time threshold,
wherein the memory management circuit is further configured to reset the total off time after performing the refresh operation on the physical erasing units.

11. The memory control circuit unit as recited in claim 10 , wherein the memory management circuit is further configured to update the total off time via the sum of the off time and the total off time if the sum of the off time and the total off time is not longer than the off time threshold, and to store the updated total off time in at least one of the physical erasing units.

12. The memory control circuit unit as recited in claim 9 , wherein the memory circuit is further configured to continue to record a refresh operation interval time after performing the refresh operation on the physical erasing units; and,
wherein the memory management circuit is further configured to perform the refresh operation on physical erasing units if the refresh operation interval time is longer than an interval time threshold.

13. The memory control circuit unit as recited in claim 9 , further comprising an error checking and correcting circuit coupled to the memory management circuit,
wherein the memory management circuit is configured to give a read command sequence to read valid data stored in a first physical erasing unit of the physical erasing units, and the valid data of the first physical erasing unit is checked by the error checking and correcting circuit,
wherein the memory management circuit is further configured to calculate a number of error bits of the valid data of the first physical erasing unit,
wherein the memory management circuit is further configured to copy the valid data of the first physical erasing unit into a second physical erasing unit of the physical erasing units if the number of error bits of the valid data of the first physical erasing unit is greater than a predetermined error bit number threshold,
wherein the memory management circuit does not copy the valid data of the first physical erasing unit into the second physical erasing unit of the physical erasing units if the number of error bits of the valid data of the first physical erasing unit is not greater than the predetermined error bit number threshold.

14. The memory c

Assignees

• Phison Electronics Corp

Inventors

• Chu Chien-Hua

Classifications

• G11C16/225

  Preventing erasure, programming or reading when power supply voltages are outside the required ranges · CPC title

• G11C16/22 Primary

  Safety or protection circuits preventing unauthorised or accidental access to memory cells · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title