Reduced off current switching transistor in an organic light-emitting diode display device

Patent metadata

Field	Value
Publication number	US-9721509-B2
Application number	US-201615169251-A
Country	US
Kind code	B2
Filing date	May 31, 2016
Priority date	Jun 20, 2014
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

An active matrix organic light emitting diode (OLED) display device includes an array of pixels, each pixel including an OLED, a driving transistor (DT) coupled to drive current through the OLED, a storage capacitor, and a scanning transistor (ST) coupled to control charge on the storage capacitor corresponding to a data voltage for said pixel. The display device also includes a timing controller configured to control the ST of each pixel to update the charge stored on the storage capacitor of each pixel at a frame rate including at least one frequency within a range of 1-10 Hertz (Hz).

First claim

What is claimed is:

1. An organic light emitting diode (OLED) display device comprising:
an active matrix OLED array comprising a plurality of pixels arranged in a row and column structure, each pixel comprising an OLED, a driving transistor (DT) coupled to drive current through the OLED, a storage capacitor, and a switching transistor (ST) coupled to control charge on the storage capacitor corresponding to a data voltage for said pixel; and
a timing controller configured to:
receive digital video data and supply the digital video data to a data driving circuit;
generate a data control signal to control timing of the data driving circuit;
generate a gate control signal to control timing of a gate driving circuit; and
wherein the data control signal and the gate control signal together control the display of the digital video data by the array by controlling the ST of each pixel to update the charge stored on the storage capacitor of each of the pixels at a frame rate including at least one frequency within a range of 1-10 Hertz (Hz).

2. The OLED display device of claim 1 , wherein each driving transistor (DT) comprises:
a DT active layer formed on a substrate, the DT active layer formed of a low-temperature polysilicon material;
a DT source and a DT drain both formed in the DT active layer;
a gate insulating layer formed on the DT active layer;
a DT gate formed on the gate insulating layer above the DT active layer;
an insulating layer formed above the DT gate;
wherein each switching transistor (ST) comprises:
a ST gate formed on the gate insulating layer, the ST gate at least partially covered by the insulating layer;
a ST active layer formed on the insulating layer above the ST gate, the ST active layer formed of an oxide semiconductor material; and
a ST source and a ST drain both contacting the ST active layer on opposite sides of the ST gate; and
wherein each OLED comprises an anode electrically coupled to the DT source, and wherein the DT gate is electrically coupled to the ST source.

3. The OLED display device of claim 2 , wherein the oxide semiconductor material is at least one selected from the group consisting of: zinc oxide (ZnO) and Gallium Indium Zinc Oxide (GIZO).

4. The OLED display device of claim 2 , wherein both the DT gate and the ST gate are formed using a same metal layer.

5. The OLED display device of claim 2 , wherein the DT further comprises:
a first ILD formed on the DT gate;
a second ILD formed on the first ILD; and
wherein a third ILD is formed on the second ILD, and
wherein the insulating layer is the third interlayer dielectric (ILD).

6. The OLED display device of claim 2 , wherein the DT further comprises:
a first ILD formed on the DT gate; and
a second ILD formed on the first ILD; and
wherein the insulating layer is the second interlayer dielectric (ILD).

7. The OLED display device of claim 2 , wherein the insulating layer physically contacts the ST gate and the ST active layer.

8. The OLED display device of claim 2 , wherein the storage capacitor of each pixel further comprises:
a first layer formed with a portion of the DT active layer; and
a second layer formed with a portion of a metal layer, the metal layer also including the DT gate and the ST gate.

9. The OLED display device of claim 8 , wherein the first layer and the second layer are separated by a portion of the gate insulating layer, wherein the portion of the gate insulating layer between the first and the second layers is formed with a substance having a high dielectric constant.

10. The OLED display device of claim 8 , wherein each pixel further comprises:
a second storage capacitor comprising:
the second layer; and
a third layer formed with a portion of a second metal layer, the second metal layer also including the DT source electrode and the DT drain electrode.

11. The OLED display device of claim 10 , wherein the second layer and the third layer are separated by a first interlayer dielectric (ILD) formed between the second layer and the third layer.

Assignees

• Lg Display Co Ltd

Inventors

• Kim Junghyeon
• Bang Hyungjin

Classifications

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2340/0435

  Change or adaptation of the frame rate of the video stream · CPC title