Adaptive multilevel binning to improve hierarchical caching

Patent metadata

Field	Value
Publication number	US-9720842-B2
Application number	US-201313772160-A
Country	US
Kind code	B2
Filing date	Feb 20, 2013
Priority date	Feb 20, 2013
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A device driver calculates a tile size for a plurality of cache memories in a cache hierarchy. The device driver calculates a storage capacity of a first cache memory. The device driver calculates a first tile size based on the storage capacity of the first cache memory and one or more additional characteristics. The device driver calculates a storage capacity of a second cache memory. The device driver calculates a second tile size based on the storage capacity of the second cache memory and one or more additional characteristics, where the second tile size is different than the first tile size. The device driver transmits the second tile size to a second coalescing binning unit. One advantage of the disclosed techniques is that data locality and cache memory hit rates are improved where tile size is optimized for each cache level in the cache hierarchy.

First claim

What is claimed is:

1. A method for calculating a tile size for a plurality of cache memories in a cache hierarchy, the method comprising:
calculating a storage capacity of a first cache memory that resides at a first level in the cache hierarchy and is associated with a corresponding first coalescing binning unit;
calculating a first tile size based on the storage capacity of the first cache memory and a first set of characteristics of data being processed in a first portion of a graphics processing pipeline;
transmitting the calculated first tile size to the corresponding first coalescing binning unit;
calculating a storage capacity of a second cache memory that resides at a second level in the cache hierarchy and is associated with a corresponding second coalescing binning unit;
calculating a second tile size based on the storage capacity of the second cache memory and a second set of characteristics of data being processed in a second portion of the graphics processing pipeline, wherein the second tile size is different than the first tile size; and
transmitting the calculated second tile size to the corresponding second coalescing binning unit.

2. The method of claim 1 , wherein the first coalescing binning unit comprises a tile coalescing unit, and the first cache memory comprises a level 1 cache memory that stores fragment data associated with raster operations.

3. The method of claim 1 , wherein the first coalescing binning unit comprises a tile coalescing unit, and the first cache memory comprises a level 1 cache memory that stores texture data associated with texturing operations.

4. The method of claim 1 , wherein the first tile size is calculated based on at least one of a quantity of samples per pixel associated with an anti-alias mode, a quantity of bytes per sample associated with one or more render targets, and a size of a texture element associated with a texture map.

5. The method of claim 1 , wherein the first tile size is modified by the first coalescing binning unit based on an angle of a graphics primitive with respect to a screen surface of a display device.

6. The method of claim 1 , wherein the second coalescing binning unit comprises a tiled caching binning unit, and the second cache memory comprises a level 2 cache memory that stores graphics primitive data.

7. The method of claim 1 , wherein the second tile size is calculated based on at least one of a quantity of samples per pixel associated with an anti-alias mode, a quantity of bytes per sample associated with one or more render targets, and a state parameter associated with a graphics processing pipeline.

8. The method of claim 1 , further comprising:
calculating a storage capacity of a third cache memory that resides at a third level in the cache hierarchy and is associated with a corresponding third coalescing binning unit;
calculating a third tile size based on the storage capacity of the third cache memory and one or more characteristics of data being processed in a third portion of the graphics processing pipeline, wherein the third tile size is different than both the first tile size and the second tile size;
transmitting the third tile size to the corresponding third coalescing binning unit.

9. The method of claim 8 , wherein the third coalescing binning unit comprises a draw call reorder unit, and the third cache memory comprises a frame buffer that stores draw call instructions associated with a 3D graphics scene.

10. The method of claim 8 , wherein the third tile size is calculated based on at least one of a size of a draw call instruction associated with a graphics object, a size of a set of attributes defining the position of the graphics object, a size of a description of a light source configured to illuminate the graphics object, and a size of a texture map associated with the graphics object.

11. The method of claim 1 , wherein the second set of characteristics comprises a second size of all data and attributes associated with a graphics primitive that intersects a second tile having the second tile size, wherein the second size is less than or equal to the storage capacity of the second cache memory.

12. The method of claim 1 , wherein the first set of characteristics comprises a first size of all data and attributes associated with a graphics primitive that intersects a first tile having the first tile size, wherein the first size is less than or equal to the storage capacity of the first cache memory.

13. A non-transitory computer-readable medium including instructions that, when executed by a processor, cause the processor to calculate a tile size for a plurality of cache memories in a cache hierarchy, by performing the steps of:
calculating a storage capacity of a first cache memory that resides at a first level in the cache hierarchy and is associated with a corresponding first coalescing binning unit;
calculating a first tile size based on the storage capacity of the first cache memory and a first set of characteristics of data being processed in a first portion of a graphics processing pipeline;
transmitting the calculated first tile size to the corresponding first coalescing binning unit;
calculating a storage capacity of a second cache memory that resides at a second level in the cache hierarchy and is associated with a corresponding second coalescing binning unit;
calculating a second tile size based on the storage capacity of the second cache memory and a second set of characteristics of data being processed in a second portion of the graphics processing pipeline, wherein the second tile size is different than the first tile size; and
transmitting the calculated second tile size to the corresponding second coalescing binning unit.

14. The non-transitory computer-readable medium of claim 13 , wherein the first coalescing binning unit comprises a tile coalescing unit, and the first cache memory comprises a level 1 cache memory that stores fragment data associated with raster operations.

15. The non-transitory computer-readable medium of claim 13 , wherein the first coalescing binning unit comprises a tile coalescing unit, and the first cache memory comprises a level 1 cache memory that stores texture data associated with texturing operations.

16. The non-transitory computer-readable medium of claim 13 , wherein the first tile size is calculated based on at least one of a quantity of samples per pixel associated with an anti-alias mode, a quantity of bytes per sample associated with one or more render targets, and a size of a texture element associated with a texture map.

17. The non-transitory computer-readable medium of claim 13 , wherein the second coalescing binning unit comprises a tiled caching binning unit, and the second cache memory comprises a level 2 cache memory that stores graphics primitive data.

18. The non-transitory computer-readable medium of claim 13 , wherein the second tile size is calculated based on at least one of a quantity of samples per pixel associated with an anti-alias mode, a quantity of bytes per sample associated with one or more render targets, and a state parameter associated with a graphics processing pipeline.

19. The non-transitory computer-readable medium of claim 13 , further comprising the steps of:
calculating a storage capacity of a third cache memory that resides at a third level in the cache hierarchy and is associated with a corresponding third coalescing binning unit;
calculating a third tile size based on the storage capacity of the third cache memory and one or more character

Assignees

• Nvidia Corp

Inventors

• Dimitrov Rouslan
• Bastos Rui
• Hakura Ziyad S
• Lum Eric B

Classifications

• G06F2212/302

  In image processor or graphics adapter · CPC title

• G06F2212/601

  Reconfiguration of cache memory · CPC title

• G06F2212/455

  Image or video data · CPC title

• G06F12/0897 Primary

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title