Biasing schemes for storage of bits in unreliable storage locations

Patent metadata

Field	Value
Publication number	US-9720612-B2
Application number	US-201514700950-A
Country	US
Kind code	B2
Filing date	Apr 30, 2015
Priority date	Apr 30, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.

First claim

We claim:

1. A non-volatile memory system comprising:
non-volatile memory;
a controller configured to:
identify a plurality of memory elements of the non-volatile memory to store data;
determine which memory elements of the plurality of memory elements are identified in the non-volatile memory system as unreliable;

bias bits of the data to be stored in the identified unreliable memory elements to a predetermined logic value using a biasing key; and
assign bit values for the biasing key in order for the biasing module to bias, using the biasing key, more than 50% of the bits to be stored in the identified unreliable memory elements to the predetermined logic value.

2. The non-volatile memory system of claim 1 , wherein the controller is further configured to:
group the bits into a plurality of bit groups, each bit group corresponding to a bit of the biasing key;
select logic values from the plurality of bit groups; and
assign the bit values for the biasing key based on the selected logic values from the plurality of bit groups.

3. The non-volatile memory system of claim 2 , wherein the controller is configured to select the logic values from the plurality of bit groups based on a majority rule basis.

4. The non-volatile memory system of claim 2 , wherein the controller is configured to group no more than a predetermined maximum number of bits into each of the plurality of bit groups.

5. The non-volatile memory system of claim 4 , wherein the predetermined maximum number is three.

6. The non-volatile memory system of claim 2 , further comprising wherein the controller is further:
configured to record logic values of the bits to be stored in the identified unreliable memory elements, and
select the logic values from the plurality of bit groups to assign the bit values for the biasing key based on the recorded logic values of the bits.

7. The non-volatile memory system of claim 2 , wherein at least one of the plurality of bit groups comprises a multi-bit bit group when a number of the bits to be stored in the identified unreliable memory elements is greater than a maximum length of the biasing key.

8. The non-volatile memory system of claim 7 , wherein the controller is configured to generate a reduced-length string of logic values based on the bits in order to generate the biasing key when the number of the bits is greater than the maximum length of the biasing key.

9. The non-volatile memory system of claim 1 , wherein the bits comprises first bits, and wherein the controller is further:
configured to:
receive the data; and
scramble second bits of the data to be stored in memory elements of the plurality of memory elements identified as reliable without scrambling the first bits to be stored in the identified unreliable memory elements.

10. The non-volatile memory system of claim 1 , wherein the non-volatile memory system comprises a card based system.

11. The non-volatile memory system of claim 1 , wherein the non-volatile memory system comprises a solid state drive.

12. The non-volatile memory system of claim 1 , wherein the non-volatile memory system comprises a hierarchical storage system.

13. A method of generating encoded data to be stored in non-volatile memory of a non-volatile memory system, the method comprising:
scrambling, with a controller, a first set of bits of data to be stored in first memory elements of non-volatile memory, the first memory elements identified in the non-volatile memory system as reliable;
biasing, with the controller, a second set of bits of the data to be stored in second memory elements of the non-volatile memory to a predetermined logic value, the second memory elements identified in the non-volatile memory system as unreliable;
generating, with the controller, parity bits for the scrambled first set of bits and the biased second set of bits to form the encoded data; and
transferring, with the controller, the encoded data to the non-volatile memory for storage.

14. The method of claim 13 , wherein biasing the second set of bits of the data comprises biasing, with the biasing module using the biasing key, more than 50% of the second set of bits to the predetermined logic value.

15. The method of claim 13 , further comprising:
grouping, with the controller, the second set of bits into a plurality of bit groups, each bit group corresponding to a bit of the biasing key;
selecting, with the controller, logic values from the plurality of bit groups; and
assigning, with the controller, bit values for the biasing key based on the selected logic values from the plurality of bit groups.

16. The method of claim 15 , wherein selecting the logic values comprises selecting, with the controller, the logic values from the plurality of bit groups based on a majority rule basis.

17. The method of claim 13 , wherein scrambling the first set of bits of data comprises scrambling the first set of bits with the controller based on a randomly generated seed.

18. The method of claim 17 , wherein the second set of bits comprises one or more bits of the seed, and wherein biasing the second set of bits comprises biasing, with the controller using the biasing key, the one or more bits of the seed.

19. The method of claim 13 , further comprising:
transferring, with the controller, the biasing key as part of the encoded data to the non-volatile memory.

20. The method of claim 19 , further comprising:
scrambling, with the controller, the biasing key,
wherein transferring the biasing key comprises transferring a scrambled version of the biasing key as part of the encoded data to the non-volatile memory.

21. A non-volatile memory system comprising:
non-volatile memory;
means for identifying a plurality of memory elements of the non-volatile memory to store data;
means for determining which memory elements of the plurality of memory elements are identified in the non-volatile memory system as unreliable;
means for biasing bits of the data to be stored in the identified unreliable memory elements to a predetermined logic value using a biasing key; and
means for assigning bit values for the biasing key in order for the biasing module to bias, using the biasing key, more than 50% of the bits to be stored in the identified unreliable memory elements to the predetermined logic value.

22. The non-volatile memory system of claim 21 , further comprising:
means for grouping the bits into a plurality of bit groups, each bit group corresponding to a bit of the biasing key;
means for selecting logic values from the plurality of bit groups; and
means for assigning the bit values for the biasing key based on the selected logic values from the plurality of bit groups.

23. The non-volatile memory system of claim 22 , wherein the means for selecting the logic values from the plurality of bit groups comprises means for selecting the logic values from the plurality of bit groups based on a majority rule basis.

24. The non-volatile memory system of claim 22 , wherein the means for grouping comprises means for grouping no more than a predetermined maximum number of bits into each of the plurality of bit groups.

25. The non-volatile memory system of claim 22 , further comprising:
means for recording logic values of the bits to be stored in the identified unreliable memory elements,
wherein the means for selecting the logic values from the plurality of bit groups comprises means for se

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Tuers Daniel
• Manohar Abhijeet
• Hsu Jonathan

Classifications

• G11C29/82

  for EEPROMs · CPC title

• G11C29/70

  Masking faults in memories by using spares or by reconfiguring · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G06F11/1004

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title