Block storage protocol to RAM bypass

Patent metadata

Field	Value
Publication number	US-9720604-B2
Application number	US-201514820236-A
Country	US
Kind code	B2
Filing date	Aug 6, 2015
Priority date	Aug 6, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

Methods and systems are provided where a memory controller for non-volatile memory transfers data to and from random access memory over a second double data rate bus, and a host system access the random access memory over a first double data rate bus. The memory controller may transfer the data in response to a command received by the memory controller from a host system via a block storage protocol bus. Alternatively or in addition, the memory controller may transfer the data as part of caching data internal to the non-volatile memory.

First claim

What is claimed is:

1. A memory device comprising:
a random access memory;
a non-volatile solid state memory;
a memory controller configured to access the non-volatile solid state memory;
a first double data rate bus coupled to the random access memory, wherein the random access memory is accessible by a host system via the first double data rate bus;
a second double data rate bus coupled to the random access memory, wherein the random access memory is accessible by the memory controller via the second double data rate bus; and
a block storage protocol interface in communication with the memory controller, wherein the block storage protocol interface and the first double data rate bus are on parallel communication paths from the host system, wherein the memory controller is configured to receive a command from the host system via the block storage protocol interface and to transfer data from the random access memory to the non-volatile solid state memory over the second double data rate bus in response to the command.

2. The memory device of claim 1 , wherein the command identifies a location of the data in the random access memory.

3. The memory device of claim 1 , wherein the memory device is in a form of a memory card.

4. The memory device of claim 1 , wherein the controller comprises an eMMC controller.

5. The memory device of claim 1 , wherein the first double data rate bus is configured to couple to an address bus of a central processing unit of the host system.

6. The memory device of claim 1 , wherein the command conforms to a data access protocol specified by a memory card standard.

7. The memory device of claim 1 , wherein the memory device includes a multi-chip package comprising the random access memory and the non-volatile solid state memory.

8. A method comprising:
receiving, at a memory controller, a command from a host system via an interconnect; and
transferring, by the memory controller, data between a non-volatile solid state memory and a random access memory, independently of a central processing unit of the host system, via a first double data rate bus in accordance with the command, wherein the data in the random access memory is accessible by the host system through a second double data rate bus, and wherein the second double data rate bus and the interconnect are arranged in parallel with respect to the host system.

9. The method of claim 8 , wherein the command complies with a block storage protocol.

10. The method of claim 8 , wherein transferring comprises writing the data to the non-volatile solid state memory from the random access memory.

11. The method of claim 8 , wherein transferring comprises reading the data from the non-volatile solid state memory and storing the data in the random access memory.

12. The method of claim 8 further comprising caching, by the memory controller, a data structure that is internal to the non-volatile solid state memory in the random access memory.

13. The method of claim 8 further comprising identifying, in the command, a memory address of the data in the random access memory.

14. The method of claim 8 further comprising identifying, prior to receiving the command, a memory address of the data in the random access memory.

15. A system comprising:
a block storage protocol interface;
a random access memory accessible via a first double data rate bus and a second double data rate bus;
a non-volatile solid state memory; and
a memory controller configured to read and write to the non-volatile solid state memory, the memory controller further configured to access the random access memory through the second double data rate bus, the memory controller further configured to cache a data structure that is internal to the non-volatile solid state memory in the random access memory, wherein the block storage protocol interface and the first double data rate bus are on parallel communication paths from a host system, wherein the memory controller is configured to receive a command from the host system via the block storage protocol interface and to transfer data from the random access memory to the non-volatile solid state memory over the second double data rate bus in response to the command.

16. The system of claim 15 , wherein the data structure is a mapping of logical data blocks to physical data blocks.

17. The system of claim 15 further comprising a multi-chip package that includes the random access memory and the non-volatile solid state memory.

18. The system of claim 15 , wherein the non-volatile solid state memory comprises flash memory.

19. The system of claim 15 , wherein the random access memory is dynamic random access memory.

20. The system of claim 15 , wherein the data structure is an error correction code structure.

21. A memory device comprising:
a random access memory;
a non-volatile solid state memory;
a memory controller configured to access the non-volatile solid state memory;
a first double data rate bus coupled to the random access memory;
a second double data rate bus coupled to the random access memory, wherein the random access memory is accessible by the memory controller via the second double data rate bus; and
a means for communicating with the memory controller in a block storage protocol, the block storage protocol being a protocol in which data is accessed by logical block addresses (LBAs), wherein the means for communicating in the block storage protocol and the first double data rate bus are on parallel communication paths from a host system, wherein the random access memory is configured to be accessed by the host system via the first double data rate bus, wherein the memory controller is configured to be accessed by the host system via the means for communicating in the block storage protocol, wherein the memory controller is configured to receive a command from the host system via the means for communicating in the block storage protocol and to transfer data between the random access memory and the non-volatile solid state memory over the second double data rate bus in response to the command.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Lemberg Alex
• Sobol Eyal
• Asfur Mahmud

Classifications

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G11C11/005 Primary

  comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells · CPC title

• G06F3/0647

  Migration mechanisms · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title