Tracking missed periodic actions across state domains

Patent metadata

Field	Value
Publication number	US-9720491-B2
Application number	US-201514752841-A
Country	US
Kind code	B2
Filing date	Jun 27, 2015
Priority date	Jun 27, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

Systems and methods may provide for determining, in a first domain that manages a state of a second domain, that the second domain is in the state and determining, in the first domain, that a periodic action has been scheduled to occur in the second domain while the second domain is in the state. Additionally, the periodic action may be documented as a missed event with respect to the second domain. In one example, documenting the periodic action as a missed event includes incrementing a missed event counter.

First claim

We claim:

1. A system comprising:
a memory controller;
a memory coupled to the memory controller;
a power management subsystem that manages a state of the memory controller, the power management subsystem comprising a scheduler apparatus that includes:
a state interface to determine that the memory controller is in the state,
a missed action detector to determine that a periodic action has been scheduled to occur in the memory controller while the memory controller is in the state, and
a missed action tracker to document the periodic action as a missed event with respect to the memory controller; and

a missed event counter, wherein the missed action tracker is to receive an acknowledgement of a completion of one or more instances of the periodic action and decrement the missed event counter in response to the acknowledgement.

2. The system of claim 1 , wherein the missed action tracker is to increment the missed event counter to document the periodic action.

3. The system of claim 2 , wherein the scheduler apparatus further includes:
a flop component to remove the memory controller from the state in response to a value of the missed event counter reaching a threshold; and
a trigger component to trigger one or more instances of the periodic action to occur in the memory controller, wherein the one or more instances are to be triggered based on the value of the missed event counter and at an increased rate relative to a default rate associated with the periodic action, and wherein the flop component is to prevent the first domain from reentering the state until the one or more instances of the periodic action have completed.

4. The system of claim 2 , wherein the scheduler apparatus further includes:
a trigger component to trigger one or more instances of the periodic action to occur in the memory controller in response to a determination that the memory controller has exited from the state, and wherein the one or more instances are to be triggered based on a value of the missed event counter and at an increased rate relative to a default rate associated with the periodic action; and
a flop component to prevent the memory controller from reentering the state until the one or more instances of the periodic action have completed.

5. The system of claim 1 , wherein the periodic action is to be prevented from occurring while the memory controller is in the state and the state is to be one of a reduced power state or an increased performance state.

6. An apparatus comprising:
a state interface to determine, in a first domain that manages a state of a second domain, that the second domain is in the state;
a missed action detector to determine, in the first domain, that a periodic action has been scheduled to occur in the second domain while the second domain is in the state;
a missed action tracker to document the periodic action as a missed event with respect to the second domain; and
a missed event counter, wherein the missed action tracker is to receive an acknowledgement of a completion of one or more instances of the periodic action and decrement the missed event counter in response to the acknowledgement.

7. The apparatus of claim 6 , wherein the missed action tracker is to increment the missed event counter to document the periodic action.

8. The apparatus of claim 7 , wherein the first domain further includes:
a flop component to remove the second domain from the state in response to a value of the missed event counter reaching a threshold; and
a trigger component to trigger one or more instances of the periodic action to occur in the second domain, wherein the one or more instances are to be triggered based on the value of the missed event counter and at an increased rate relative to a default rate associated with the periodic action, and wherein the flop component is to prevent the second domain from reentering the state until the one or more instances of the periodic action have completed.

9. The apparatus of claim 7 , wherein the first domain further includes:
a trigger component to trigger one or more instances of the periodic action to occur in the second domain in response to a determination that the second domain has exited from the state, and wherein the one or more instances are to be triggered based on a value of the missed event counter and at an increased rate relative to a default rate associated with the periodic action; and
a flop component to prevent the second domain from reentering the state until the one or more instances of the periodic action have completed.

10. The apparatus of claim 6 , wherein the periodic action is to be prevented from occurring while the second domain is in the state and the state is to be one of a reduced power state or an increased performance state.

11. A method comprising:
determining, in a first domain that manages a state of a second domain, that the second domain is in the state;
determining, in the first domain, that a periodic action has been scheduled to occur in the second domain while the second domain is in the state;
documenting the periodic action as a missed event with respect to the second domain, receiving an acknowledgement of a completion of one or more instances of the periodic action; and
decrementing a missed event counter in response to the acknowledgement.

12. The method of claim 11 , wherein documenting the periodic action includes incrementing a missed event counter.

13. The method of claim 12 , further including:
removing the second domain from the state in response to a value of the missed event counter reaching a threshold;
triggering one or more instances of the periodic action to occur in the second domain, wherein the one or more instances are triggered based on the value of the missed event counter and at an increased rate relative to a default rate associated with the periodic action; and
preventing the second domain from reentering the state until the one or more instances of the periodic action have completed.

14. The method of claim 12 , further including:
triggering one or more instances of the periodic action to occur in the second domain in response to a determination that the second domain has exited from the state, wherein the one or more instances are triggered based on a value of the missed event counter and at an increased rate relative to a default rate associated with the periodic action; and
preventing the second domain from reentering the state until the one or more instances of the periodic action have completed.

15. The method of claim 11 , wherein the periodic action is prevented from occurring while the second domain is in the state and the state is one of a reduced power state or an increased performance state.

16. At least one non-transitory computer readable storage medium comprising a set of instructions, which when executed by a computing system, cause the computing system to:
determine, in a first domain that manages a state of a second domain, that the second domain is in the state;
determine, in the first domain, that a periodic action has been scheduled to occur in the second domain while the second domain is in the state;
document the periodic action as a missed event with respect to the second domain;
receive an acknowledgement of a completion of one or more instances of the periodic action; and
decrement a missed event counter in response to the acknowledgement.

17. The at least one non-transitory computer readable storage medium of claim 16 , wherein the instructions, when executed, cause a computing system to increment a m

Assignees

• Intel Corp

Inventors

• Mulla Dean
• Borkowski Daniel G
• Sistla Krishnakanth V
• Wu Victor
• Luthra Manev

Classifications

• G06F1/3225 Primary

  of memory devices · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F1/3237

  by disabling clock generation or distribution · CPC title

• G06F1/3296 Primary

  by lowering the supply or operating voltage · CPC title

• G06F3/0653

  Monitoring storage devices or systems · CPC title