Method and device for noise reduction in multi-frequency clocking environment

Patent metadata

Field	Value
Publication number	US-9720486-B2
Application number	US-201514865928-A
Country	US
Kind code	B2
Filing date	Sep 25, 2015
Priority date	Sep 25, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A device and method of operating a synchronous frequency processing environment served by a common power source and common clock source. The method includes operating the processing environment to have a first power consumption. The method further includes determining a first synchronous frequency processing domain within the processing environment where it is desired to implement a first clock frequency alteration in a clock signal for the first synchronous frequency processing domain. The first clock frequency alteration generates an associated first alteration in a power consumption from the first synchronous frequency processing domain. The method further includes determining a second clock frequency alteration to a clock signal for a second synchronous frequency processing domain of the processing environment. The second clock frequency alteration is determined so as to reduce a change in the first power consumption caused by the first alteration in power consumption.

First claim

What is claimed is:

1. A method of operating a synchronous frequency processing environment served by a common power source and common clock source including:
operating the processing environment to have a first power consumption;
determining a first synchronous frequency processing domain within the processing environment where it is desired to implement a first clock frequency alteration in a clock signal for the first synchronous frequency processing domain; the first clock frequency alteration generating an associated first alteration in a power consumption from the first synchronous frequency processing domain; and
determining a second clock frequency alteration to a clock signal for a second synchronous frequency processing domain of the processing environment, the second clock frequency alteration being determined so as to reduce a change in the first power consumption caused by the first alteration in power consumption.

2. The method of claim 1 , further including determining the first power consumption alteration associated with the first clock alteration.

3. The method of claim 1 , wherein the first alteration includes skipping a clock pulse; further wherein the second clock alteration includes adding clock pulses.

4. The method of claim 3 , wherein the first synchronous frequency processing domain has a first size and the second synchronous frequency processing domain has a second size, wherein determining the at least a second clock frequency alteration includes determining the relative sizes of the first and second synchronous frequency processing domains.

5. The method of claim 4 , wherein the proportion of the second clock frequency alteration to the first clock frequency alteration approximates the proportion of the size of the second frequency processing domain to the first frequency processing domain.

6. The method of claim 1 , wherein the second clock frequency alteration is an inversion of the second clock signal.

7. The method of claim 1 , further including determining a third clock frequency alteration to a third clock signal for a third synchronous frequency processing domain, the third clock frequency alteration being determined to at least partially offset a first power consumption alteration caused by the first clock frequency alteration.

8. The method of claim 1 , wherein the first and second synchronous frequency domains are portions of a common processor.

9. The method of claim 1 , wherein the first and second synchronous frequency domains are distinct processors.

10. A power distributor including:
a clock signal output carrying first clock signal instructions for a first synchronous frequency domain powered by a first power source and second clock signal instructions for a second synchronous frequency domain powered by the first power source, the first and second synchronous frequency domains providing a first power draw on the first power source; and
instructions, that when executed by the power distributor provide that an alteration to the first clock signal is accompanied with an alteration to a the second clock signal that reduces any impact that the alteration to the first clock signal has on the first power draw.

11. The power distributor of claim 10 , wherein the alteration to the first clock signal includes skipping a clock pulse; further wherein the alteration to the second clock signal includes adding clock pulses.

12. The power distributor of claim 10 , wherein the first synchronous frequency domain has a first size and the second synchronous frequency domain has a second size, wherein determining the at least a second clock alteration includes determining the relative sizes of the first and second portions.

13. The power distributor of claim 10 , further including instructions that when executed by the power distributor determine a third clock alteration to a third clock signal for a third synchronous frequency processing domain, the third clock alteration being determined to at least partially offset the first power consumption alteration.

14. A non-transitive computer readable media having instructions thereon, that when interpreted by a processor, cause the processor to:
operate a synchronous frequency processing environment served by a common power source and common clock source processing environment to have a first power consumption;
determine a first synchronous frequency processing domain within the processing environment where it is desired to implement a first clock frequency alteration in a clock signal for the first synchronous frequency processing domain; the first clock frequency alteration generating an associated first alteration in a power consumption therefrom; and
determine a second clock frequency alteration to a clock signal for a second synchronous frequency processing domain of the processing environment, the second clock frequency alteration being determined so as to reduce a change in the first power consumption caused by the first alteration in power consumption.

15. The non-transitive computer readable media of claim 14 , wherein the first alteration includes skipping a clock pulse; further wherein the second clock alteration includes adding clock pulses.

16. The non-transitive computer readable media of claim 14 , wherein the first synchronous frequency processing domain has a first size and the second synchronous frequency processing domain has a second size, wherein determining the at least a second clock frequency alteration includes determining the relative sizes of the first and second synchronous frequency processing domains.

17. The non-transitive computer readable media of claim 16 , wherein the proportion of the second clock frequency alteration to the first clock frequency alteration approximates the proportion of the size of the second frequency processing domain to the first frequency processing domain.

18. The non-transitive computer readable media of claim 14 , wherein the second clock frequency alteration is an inversion of the second clock signal.

19. The non-transitive computer readable media of claim 14 , wherein the instructions further cause the processor to determine a third clock frequency alteration to a third clock signal for a third synchronous frequency processing domain, the third clock frequency alteration being determined to at least partially offset a first power consumption alteration caused by the first clock frequency alteration.

20. The non-transitive computer readable media of claim 14 , wherein the first and second synchronous frequency domains are portions of a common processor.

Assignees

• Advanced Micro Devices Inc
• Ati Technologies Ulc

Inventors

• Socarras Angel E
• Guo Fei

Classifications

• G06F1/06

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title