Methods, apparatuses, and systems for deskewing link splits

Patent metadata

Field	Value
Publication number	US-9720439-B2
Application number	US-201514866866-A
Country	US
Kind code	B2
Filing date	Sep 26, 2015
Priority date	Sep 26, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

Systems, methods, and apparatuses are described for deskewing between multiple lane groups of deskewed data streams. Multiple distinct and deskewed lane groups can be aligned by utilizing an inter-group synchronized set of counters. The counters supply a way to measure the time delta (counter difference) in clocks between the multiple streams. Using this delta, one or more streams can be stalled to align the multiple streams. The counter values are communicated between the multiple groups in a way that they align to set data stream markers. These fixed markers and the breaking up of the counters in relation to the periodicity of the markers allows for a robust way to compare the multiple streams and calculate an accurate time delta.

First claim

What is claimed is:

1. A method comprising:
receiving, from a local counter, a first counter value, the first counter value representing a position of a first stream of deskewed data on a first multi-lane link compliant with a peripheral component interface express (PCIe) protocol;
receiving, from a communications interface associated with a second stream of deskewed data, a second counter value, the second counter value representing a position of the second stream of deskewed data on a second multi-lane link compliant with a peripheral component interface express (PCIe) protocol;
obtaining a data portion of the first counter value based on a lookup of an address portion of the first counter value using an address portion of the second counter value;
comparing the data portion of the first counter value with a data portion of the second counter value; and
stalling the first stream of deskewed data from transmission on a multi-lane PCIe link when the data portion of the first counter value is less than the data portion of the second counter value.

2. The method of claim 1 , further comprising sending a counter value difference to the second stream of deskewed data when the data portion of the second counter value is less than the data portion of the first counter value, the counter value difference representing a difference between the data portion of the first counter value and the data portion of the second counter value and indicating that the second stream of deskewed data should be stalled.

3. The method of claim 1 , further comprising clearing a storage logic of the address portion of the first counter value and the data portion of the first counter value in response to stalling the first stream of deskewed data.

4. The method of claim 1 , further comprising signaling that the first stream of deskewed data and the second stream of deskewed data are time-aligned when the data portion of the first counter value is equal to the data portion of the second counter value.

5. The method of claim 1 , further comprising identifying a delta between the data portion of the first counter value and the data portion of the second counter value, and stalling the first stream of deskewed data based on the delta.

6. A deskew apparatus comprising:
a first counter operation logic implemented at least in part on hardware to:
receive, from a local counter, a first counter value representing a position of a first stream of deskewed data on a first multi-lane link compliant with a peripheral component interface express (PCIe) protocol (multi-lane PCIe link), and

a second counter operation logic implemented at least on hardware to:
receive, from a communications interface associated with a second stream of deskewed data, a second counter value representing a position of a second stream of deskewed data on a second multi-lane PCIe link, and

memory logic implemented at least on hardware to:
lookup an address portion of the first counter value from a random access memory based on an address portion of the second counter value; and

a comparator logic implemented at least in hardware to:
compare a data portion of the first counter value with a data portion of the second counter value, and
output a count difference between the data portion of the first counter value and the data portion of the second counter value, the count difference representing a skew between the first stream of deskewed data and the second stream of deskewed data.

7. The apparatus of claim 6 , comprising further comparator logic to send a counter value difference to the second stream of deskewed data when the data portion of the second counter value is less than the data portion of the first counter value, the counter value difference indicating the second stream of deskewed data should be stalled from transmission on the second multi-lane PCIe link.

8. The apparatus of claim 6 , the first counter operation logic comprising further logic implemented at least in part on hardware to:
separate the address portion of the first counter value from the data portion of the first counter value; and
wherein the first counter operation logic comprising further logic implemented at least in part on hardware to:
separate the second counter value into an address portion of the second counter value and into a data portion of the second counter value,
wherein the data portion of the first counter value is stored with the address portion of the first counter value, and wherein the second counter value is used to lookup the address portion of the first counter value to identify the data portion of the first counter value.

9. The apparatus of claim 6 , comprising further comparator logic to signal that the first stream of deskewed data and the second stream of deskewed data are time-aligned when the data portion of the first counter value is equal to the data portion of the second counter value.

10. The apparatus of claim 6 , comprising further comparator logic to identify a delta between the data portion of the first counter value and the data portion of the second counter value, and stall the first stream of deskewed data based on the delta.

11. An apparatus comprising:
a deskew control logic implemented at least in part in hardware to:
compare a data portion of a first counter value to a data portion of a second counter value, the first counter value representing a skew of a first stream of data on a first multi-lane link compliant with a peripheral component interface express (PCIe) protocol (PCIe link) and the second counter value representing a skew of a second stream of data on a second multi-lane PCIe link, and
stall one of the first stream of data from transmission on the first multi-lane PCIe link or the second stream of data from transmission on the second multi-lane PCIe link based on a comparison of the data portion of the first counter value to the data portion of the second counter value;
the apparatus further comprising:
a data storage logic implemented at least in hardware to:
store an address portion of the first counter value and the data portion of the first counter value; and
a local counter operator logic implemented at least in part in hardware to receive the first counter value and to output, to the data storage logic, the address portion of the first counter value and the data portion of the first counter value.

12. The apparatus of claim 11 , further comprising a far counter operator logic implemented at least in part in hardware to receive the second counter value and to output, to the data storage logic, an address portion of the second counter value and to output, to a comparator logic, the data portion of the second counter value.

13. The apparatus of claim 11 , further comprising a comparator logic, implemented at least in part in hardware, to compare the data portion of the first counter value to the data portion of the second counter value, and to output a stall signal to the deskew control logic based on the comparison of the data portion of the first counter value to the data portion of the second counter value.

14. The apparatus of claim 11 , wherein the comparator logic receives the data portion of the first counter value from the data storage logic and receives the data portion of the second counter value from the far counter operator logic.

15. A system comprising:
a data storage logic implemented at least in part in hardware to:
lookup an address portion of a first counter value based on an address portion of a second counter value, the first counter value representing a position in time of a first stream of data on a firs

Assignees

• Intel Corp

Inventors

• Tennant Bruce A

Classifications

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title