Control device

Patent metadata

Field	Value
Publication number	US-9719481-B2
Application number	US-201314646174-A
Country	US
Kind code	B2
Filing date	Oct 25, 2013
Priority date	Nov 26, 2012
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

The invention, while reducing noise, suppresses a load increase in a processor and a delay in drive control. An engine control unit includes a processor, a driving circuit including a switching element to drive a load such as a fuel injector and an ignition device, and a communication circuit that transmits control signals from the processor to the driving circuit via serial communication. The control signals each include a command frame for controlling the driving circuit and a data frame for driving the load. If a predetermined bits in each of the data frames received from the processor at predetermined time intervals are determined to be the same twice in succession, the engine control unit changes a state of a driving signal ‘Drive’ for driving the load and thereby changes an operating state of the switching element.

First claim

The invention claimed is:

1. An engine control device comprising:
a processor;
a driving circuit including a plurality of drivers that drive electrical loads of the engine; and
a communication circuit that transmits a plurality of control signals from the processor to the driving circuit via serial communication;
wherein the driving circuit;
receives the plurality of control signals over a plurality of time frames, wherein each of the plurality of time frames is received for a predetermined interval of time and the predetermined interval of time is equal to or less than a target value obtained by dividing an amount of time needed for a crankshaft to revolve through a unit angle at a maximum allowable revolving speed of the engine by a first predetermined number of times,
determines a value for each of the plurality of control signals, and
changes an operating state of one or more of the drivers if the value is determined the first predetermined number of times in succession.

2. The engine control device according to claim 1 , wherein the communication circuit includes a plurality of data registers and each of the plurality of registers stores either a first value or a second value; and
wherein the communication circuit further:
receives a clock signal, wherein the clock signal is a timing signal that alternates between a high value and a low value at fixed intervals of time, and
counts a number of high values of the clock signal received while the determined value is a particular value for each of the plurality of control signals, and stores, for each of the plurality of control signals, either the first value or the second value in the one or more of the plurality of data registers based on the number of high values that are counted for each of the plurality of signals.

3. The engine control device according to claim 1 , wherein:
the communication circuit includes a plurality of data registers and each of the plurality of registers stores either a first value or a second value,
one or more ignition devices of the engine correspond to a particular data register from the plurality of data registers, and
each ignition device is activated when the particular data register stores the first value.

4. The engine control device according to claim 3 , wherein
each ignition device is deactivated when the particular data register stores the second value.

5. The engine control device of claim 1 , further comprising:
a combinational determination circuit communicatively coupled to the communication circuit;
a control circuit communicatively coupled to the combinational determination circuit; and
a plurality of ignitor pre-driver circuits, wherein each of the ignitor pre-driver circuits is communicatively coupled to the control circuit and the plurality of drivers.

6. The engine control device of claim 5 , wherein the communication circuit includes a plurality of data registers and each of the plurality of registers stores either a first value or a second value; and
wherein the communication circuit:
receives the plurality of control signals from the processor, wherein each of the plurality of control signals is received over the plurality of time frames,
stores, for each of the plurality of control signals, the first value in one or more of the plurality of data registers, when a high value is received for a predetermined number of consecutive time frames, and
stores, for each of the plurality of control signals, the second value in one or more of the plurality of data registers, when a low value is received for the predetermined number of consecutive time frames;
wherein the combinational determination circuit:
reads the plurality of data registers,
compares the plurality of data registers to a table of ignition impacts to produce a comparison result, wherein the table of ignition impacts indicate one or more effects of multi-cylinder simultaneous ignition upon the engine, and
transmits, for each of the plurality of registers, an enable signal to the control circuit based on the comparison; and
wherein the control circuit further:
receives the enable signal for each of the plurality of registers, and
selectively activates a drive signal to each of the plurality of ignitor pre-driver circuits based on the enable signal.

7. The engine control device of claim 6 , wherein the combinational determination circuit further stores, values for each of the plurality of data registers, in a memory on a condition that the comparison result indicates normal operation; and
wherein the enable signal is based on the values stored in the memory on condition that the comparison result indicates abnormal operation.

Assignees

• Hitachi Automotive Systems Ltd

Inventors

• Oyama Katsuya
• Sato Chihiro
• Watanabe Mitsuhiko

Classifications

• F02P9/002 Primary

  Control of spark intensity, intensifying, lengthening, suppression (by means of current control in the storage devices F02P3/05, F02P3/09, during starting F02P15/12) · CPC title

• F02D41/26

  using computer, e.g. microprocessor · CPC title

• F02D2250/12

  Timing of calculation, i.e. specific timing aspects when calculation or updating of engine parameter is performed · CPC title

• F02D41/266

  the computer being backed-up or assisted by another circuit, e.g. analogue · CPC title

• F02P3/055

  with protective means to prevent damage to the circuit, {e.g. semiconductor devices} or the ignition coil · CPC title