Semiconductor structure and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-9718682-B2
Application number	US-201615222006-A
Country	US
Kind code	B2
Filing date	Jul 28, 2016
Priority date	Jul 31, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A method for fabricating a semiconductor structure includes providing a substrate with a first surface and a second surface, wherein at least one soldering pad is formed on the first surface of the substrate. The method also includes forming at least one via to expose each soldering pad by etching the substrate from the second surface, forming a seed layer to cover the second surface of the substrate and the sidewall and the bottom surfaces of each via, and then forming a redistribution metal layer over a portion of the seed layer formed on the sidewall and the bottom surfaces of each via and the second surface of the substrate surrounding each via. The method further includes alternately performing a pre-wetting process and a chemical etching process to completely remove the portion of the seed layer not covered by the redistribution metal layer.

First claim

What is claimed is:

1. A method for fabricating a semiconductor structure, comprising:
providing a semiconductor substrate with a first surface and a second surface opposite to the first surface, wherein at least one soldering pad is formed on the first surface of the semiconductor substrate;
forming at least one via in the semiconductor substrate to expose each soldering pad by etching the semiconductor substrate from the second surface of the semiconductor substrate;
forming a seed layer to cover a sidewall surface and a bottom surface of each via and the second surface of the semiconductor substrate;
forming a redistribution metal layer to cover a portion of the seed layer formed on the sidewall and the bottom surfaces of each via and on a portion of the second surface of the semiconductor substrate surrounding each via;
performing a pre-wetting process by spraying a diluting agent onto the seed layer and the redistribution metal layer to let each via retain a portion of the diluting agent;
performing a chemical etching process right after the pre-wetting process by spraying an etch solution onto the seed layer and the redistribution metal layer to remove a portion of the seed layer not covered by the redistribution metal layer; and
repeating the pre-wetting process and the chemical etching process alternately until the portion of the seed layer not covered by the redistribution metal layer is completely removed.

2. The method for fabricating the semiconductor structure according to claim 1 , wherein forming the redistribution metal layer further includes:
forming a mask layer on the seed layer with an opening to expose a portion of the seed layer formed on the sidewall and the bottom surfaces of each via and a portion of the surface of the seed layer surrounding each via;
performing an electroplating process to form the redistribution metal layer covering the portion of seed layer exposed by the opening of the mask layer; and
removing the mask layer.

3. The method for fabricating the semiconductor structure according to claim 1 , wherein:
a plurality of device components including photosensitive areas, MEMS transistors, and integrated circuits are formed on the first surface of the semiconductor substrate;
the plurality of device components are electrically connected to corresponding soldering pads of the at least one soldering pad formed on the first surface of the semiconductor substrate.

4. The method for fabricating the semiconductor structure according to claim 3 , wherein:
a plurality of photosensitive areas are formed on the first surface of the semiconductor substrate;
the at least one soldering pad is formed on the first surface of the semiconductor substrate surrounding each photosensitive area;
a plurality of embankment structures are formed on the first surface of the semiconductor substrate to surround the plurality of photosensitive areas;
a plurality of cavities are formed by the plurality of embankment structures, wherein each cavity exposes a corresponding photosensitive area; and
a glass board is placed on the plurality of embankment structures to seal openings of the cavities formed in the embankment structures.

5. The method for fabricating the semiconductor structure according to claim 4 , wherein performing the pre-wetting process and the chemical etching process further includes:
holding the glass board by using a clamping unit in an etching apparatus with an opening of each via formed in the semiconductor substrate facing downwards; and
driving the clamping unit to let the semiconductor substrate spin.

6. The method for fabricating the semiconductor structure according to claim 5 , wherein:
the diluting agent used in the pre-wetting process is deionized water (DI-water) or organic solvent; and
the diluting agent is sprayed onto the surfaces of the seed layer and the redistribution metal layer from down to up.

7. The method for fabricating the semiconductor structure according to claim 6 , wherein, during the pre-wetting process:
the diluting agent used in the pre-wetting process is DI-water;
a spin speed of the semiconductor substrate is in a range of 250 rpm to 350 rpm;
a pre-wetting time is in a range of 1 min to 2 min; and
an environmental temperature is in a range of 22° C. to 24° C.

8. The method for fabricating the semiconductor structure according to claim 5 , wherein, during the chemical etching process,
the etch solution is sprayed onto the surfaces of the seed layer and the redistribution metal layer from down to up;
a spin speed of the semiconductor substrate is in a range of 250 rpm to 350 rpm;
an etching time is in a range of 30 s to 50 s; and
an environmental temperature is in a range of 22° C. to 24° C.

9. The method for fabricating the semiconductor structure according to claim 5 , wherein the pre-wetting process and the chemical etching process are alternately performed for 4 to 10 times.

10. The method for fabricating the semiconductor structure according to claim 5 , wherein a spin speed of the semiconductor substrate during the pre-wetting process is the same as a spin speed of the semiconductor substrate during the chemical etching process.

11. The method for fabricating the semiconductor structure according to claim 1 , wherein the seed layer has a double-layer structure including a metal adhesion layer and a seed layer formed on the metal adhesion layer.

12. The method for fabricating the semiconductor structure according to claim 11 , wherein a thickness of the seed layer formed on the semiconductor substrate is larger than a thickness of the seed layer formed on the sidewall and the bottom surfaces of the via.

13. The method for fabricating the semiconductor structure according to claim 11 , wherein the metal adhesion layer and the seed layer is formed by sputtering.

14. The method for fabricating the semiconductor structure according to claim 1 , wherein the redistribution metal layer is made of Cu.

15. The method for fabricating the semiconductor structure according to claim 1 , wherein a thickness of the redistribution metal layer formed on the second surface of the semiconductor substrate is larger than a thickness of the redistribution metal layer formed in the via.

16. The method for fabricating the semiconductor structure according to claim 1 , after completely removing the portion of the seed layer not covered by the redistribution metal layer, further including:
cleaning the surface of the redistribution metal layer and the second surface of the semiconductor substrate through a cleaning process using DI-water; and
removing water residue on the redistribution metal layer and the second surface of the semiconductor substrate through a drying process using nitrogen gas.

17. The method for fabricating the semiconductor structure according to claim 1 , after completely removing the portion of the seed layer not covered by the redistribution metal layer, further including:
forming an isolation material layer to cover the redistribution metal layer and fill the via;
forming an opening in the isolation material layer to expose a portion of the redistribution metal layer on the second surface of the semiconductor substrate;
forming a bulging lower metal layer on the surface of the portion of the redistribution metal layer exposed in the opening; and
forming a metal bump on the bulging lower metal layer.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Ren Peng

Classifications

• H10P72/0448

  Apparatus for applying a liquid, a resin, an ink or the like · CPC title

• H10P72/0418

  for etching · CPC title

• H10P72/76

  using mechanical means, e.g. clamps or pinches · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/01235

  by plating, e.g. electroless plating or electroplating · CPC title