Semiconductor structure and manufacturing method thereof

US9718677B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-9718677-B1
Application numberUS-201615000521-A
CountryUS
Kind codeB1
Filing dateJan 19, 2016
Priority dateJan 19, 2016
Publication dateAug 1, 2017
Grant dateAug 1, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

In the present disclosure a semiconductor device comprises a plate including a plurality of apertures. The semiconductor device also comprises a membrane disposed opposite to the plate and including a plurality of corrugations, a dielectric surrounding and covering an edge of the membrane, and a substrate. The semiconductor device further includes a metallic conductor comprising a first portion extending through the dielectric, and a second portion over the substrate, where the second portion is bonded with the first portion.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device, comprising: a plate including a plurality of apertures; a membrane disposed opposite to the plate and including a plurality of corrugations on a surface; a first dielectric surrounding and covering an edge of the membrane; a substrate; a second dielectric between the substrate and the first dielectric; and a metallic conductor, comprising a first portion extending through the first dielectric along a first central axis of the first portion; and a second portion over the substrate, an end of the second portion extending through the second dielectric along a second central axis of the end, wherein the second portion is bonded with the first portion and the second central axis is offset from the first central axis. 2. The semiconductor device of claim 1 , wherein the membrane is configured to be displaceable relative to the plate. 3. The semiconductor structure of claim 1 , wherein the membrane is within a cavity defined by the plate and the membrane. 4. The semiconductor structure of claim 1 , wherein the first portion conductor includes one of gold, tin, silicon, copper and tin copper alloy. 5. The semiconductor structure of claim 1 , wherein the second portion conductor includes one of gold, tin, silicon, copper and tin copper alloy. 6. The semiconductor structure of claim 1 , wherein the membrane is sensitive to an acoustic pressure. 7. The semiconductor structure of claim 1 , wherein the first portion conductor is electrically coupled to the membrane. 8. The semiconductor structure of claim 1 , wherein the plate comprises a silicon-on-insulator layer, polysilicon, oxide, or epitaxial silicon. 9. The semiconductor structure of claim 1 , wherein the second portion conductor is configured as a loop. 10. The semiconductor structure of claim 1 , wherein each of the plurality of corrugations is protruded from membrane and toward the plate. 11. A monolithic sensor, comprising: a micro-electro mechanical system (MEMS) device comprising: a plate including a plurality of apertures; a membrane disposed opposite to the plate and including a plurality of corrugations; a first conductor disposed below the plate and extending along a first central axis of the first conductor, and a first cavity between the plate and the membrane; and a complementary metal oxide semiconductor (CMOS) device comprising: a substrate; an interconnect disposed over the substrate and a second conductor electrically coupled to the interconnect and extruded from the interconnect toward the membrane along a second central axis of the second conductor, wherein the first conductor is connected with the second conductor in a metal bond manner and the first central axis is in parallel but not aligned with the second central axis. 12. The monolithic sensor of claim 11 , wherein a total thickness from the MEMS to the CMOS device is less than about 200 um. 13. The monolithic sensor of claim 11 , wherein the plate is stationary and the membrane is movable within the first cavity and relative to the plate. 14. The monolithic sensor of claim 11 , wherein the MEMS device includes a dielectric disposed around a peripheral portion of the membrane. 15. The monolithic sensor of claim 11 , wherein the CMOS device includes a dielectric between the interconnect and the first conductor, wherein a portion of the second conductor is partially interposed between the interconnect and the first conductor. 16. The monolithic sensor of claim 11 , wherein the plate has a thickness of about 0.3 um to about 50 um. 17. The monolithic sensor of claim 11 , wherein the plate is disposed away from the membrane in a distance of about 0.1 um to about 5 um. 18. A semiconductor device, comprising: a plate including a plurality of apertures; a movable membrane including a plurality of corrugations; a first cavity between the plate and the movable membrane; a substrate; a first dielectric between the plate and the substrate; a metallic conductor, comprising a first portion being in contact with the first dielectric; and a second portion over the substrate, wherein the second portion is bonded with the first portion, wherein a central axis shared by the first portion and the second portion staggers conformally to the first portion and the second portion. 19. The semiconductor device of claim 18 , wherein a sidewall of the first portion is partially exposed from the first dielectric. 20. The semiconductor device of claim 18 , further comprising a second dielectric between the substrate and the first dielectric, wherein the second portion is surrounded by the second dielectric.

Assignees

Inventors

Classifications

  • B81B3/0027Primary

    Structures for transforming mechanical energy, e.g. potential energy of a spring into translation, sound into translation · CPC title

  • corrugated, pleated or ribbed · CPC title

  • Microphones or microspeakers · CPC title

  • for making multi-layered devices, film deposition or growing · CPC title

  • Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9718677B1 cover?
In the present disclosure a semiconductor device comprises a plate including a plurality of apertures. The semiconductor device also comprises a membrane disposed opposite to the plate and including a plurality of corrugations, a dielectric surrounding and covering an edge of the membrane, and a substrate. The semiconductor device further includes a metallic conductor comprising a first portion…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification B81B3/0027. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Aug 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).