DC impedance detection circuit and method for speaker

Patent metadata

Field	Value
Publication number	US-9716954-B2
Application number	US-201614997699-A
Country	US
Kind code	B2
Filing date	Jan 18, 2016
Priority date	Jan 19, 2015
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

A DC impedance detection circuit can include: an integration time generation circuit configured to generate an integration time signal in accordance with a current flowing through a speaker, where the current of a speaker at a beginning time of each active time interval of the integration time signal is the same as that at an ending time of the active time interval; a current integration circuit configured to integrate the current of the speaker in the active time interval, and to generate a current integration signal; a voltage integration circuit configured to integrate a voltage of the speaker in the active time interval, and to generate a voltage integration signal; and where a ratio between the voltage integration signal and the current integration signal is configured as a DC impedance of the speaker in the active time interval.

First claim

What is claimed is:

1. A method of detecting a DC impedance of a speaker, the method comprising:
a) generating a current integration signal by integrating a current of said speaker in an integration time interval;
b) generating a voltage integration signal by integrating a voltage of said speaker in said integration time interval;
c) generating a DC impedance of said speaker in said integration time interval by calculating a ratio between said voltage integration signal and said current integration signal; and
d) said integration time interval being a time interval during operation of said speaker, wherein said current of said speaker at a beginning time of said integration time interval is the same as that at an ending time of said integration time interval.

2. The method of claim 1 , wherein said integration time interval comprises at least one time at which said current of said speaker is the same as that at said beginning time.

3. The method of claim 1 , wherein:
a) said speaker is driven by a class D audio amplifier having a first and second half bridge switching circuits configured to provide first and second voltages to two terminals of said speaker; and
b) said integration time interval comprises multiple switching periods of said class D audio amplifier.

4. The method of claim 3 , further comprising:
a) generating a current time parameter of said switching period by multiplying, in each switching period of said integration time interval, an average value of said current of said speaker at said beginning time of said switching period and said current of said speaker at said ending time of said switching period with a length of said switching period; and
b) generating said current integration signal by summing each of said current time parameters of each of said switching periods in said integration time interval.

5. The method of claim 4 , wherein said integrating said voltage of said speaker comprises:
a) generating first, second, and third voltage time parameters, by multiplying, in each switching period of said integration time interval, said voltage of said speaker with lengths of first, second, and third time intervals;
b) generating a voltage time parameter of said switching period by summing said first, second, and third voltage time parameters;
c) wherein said first voltage is greater than said second voltage in said first time interval, said first voltage is the same as said second voltage in said second time interval, and said first voltage is less than said second voltage in said third time interval; and
d) generating said voltage integration signal by summing each of said voltage time parameters of said switching periods in said integration time interval.

6. The method of claim 1 , further comprising filtering said current and voltage of said speaker prior to said integrating said current and voltage of said speaker.

7. The method of claim 6 , wherein said determining said integration time interval comprises:
a) sampling said current of said speaker at said beginning time;
b) after a delay time, detecting said current of said speaker, and comparing against said current at said beginning time; and
c) configuring a time as said ending time of said integration time interval when said current of said speaker is the same as that at said beginning time.

8. A DC impedance detection circuit, comprising:
a) an integration time generation circuit configured to generate an integration time signal in accordance with a current flowing through a speaker, wherein said current of a speaker at a beginning time of each active time interval of said integration time signal is the same as that at an ending time of said active time interval;
b) a current integration circuit configured to integrate said current of said speaker in said active time interval, and to generate a current integration signal;
c) a voltage integration circuit configured to integrate a voltage of said speaker in said active time interval, and to generate a voltage integration signal; and
d) wherein a ratio between said voltage integration signal and said current integration signal is configured as a DC impedance of said speaker in said active time interval.

9. The DC impedance detection circuit of claim 8 , further comprising a division circuit configured to calculate said ratio between said voltage and said current integration signals, and to generate said DC impedance of said speaker.

10. The DC impedance detection circuit of claim 8 , further comprising a current sampling circuit configured to generate a sampling signal that represents said current of said speaker.

11. The DC impedance detection circuit of claim 10 , said active time interval of said integration time signal comprises at least one time at which said current of said speaker is the same as that at said beginning time.

12. The DC impedance detection circuit of claim 11 , wherein said integration time signal generation circuit comprises:
a) an RS flip flop having a set terminal configured to receive a clock signal, a reset terminal configured to receive an output signal of an identity comparator, and an output terminal configured to provide said integration time signal;
b) said identity comparator having a first input terminal configured to receive said sampling signal, and a second input terminal coupled to a first terminal of a sampling capacitor, wherein a second terminal of said sampling capacitor is coupled to ground;
c) a sampling switch having a first terminal coupled to said first terminal of said sampling capacitor, and a second terminal configured to receive said sampling signal, wherein said sampling switch is controllable by said clock signal; and
d) a shielding switch coupled between said output terminal of said identity comparator and said reset terminal.

13. The DC impedance detection circuit of claim 8 , wherein said integration time generation circuit further comprises a delay trigger circuit configured to generate a clearing signal in accordance with said integration time signal, wherein said clearing signal is activated after a delay time has elapsed after said integration time signal goes inactive.

14. The DC impedance detection circuit of claim 13 , wherein each of said current integration circuit and said voltage integration circuit comprises:
a) an integration control switch coupled between a controllable current source and a first terminal of an integration capacitor having a second terminal coupled to ground; and
b) a clearing control switch coupled in parallel with said integration control switch, wherein a voltage across said integration capacitor is configured as said current integration signal when said controllable current source is controlled by said current of said speaker in said current integration circuit, and wherein said voltage across said integration capacitor is configured as said voltage integration signal when said controllable current source is controlled by said voltage of said speaker in said voltage integration circuit.

15. The DC impedance detection circuit of claim 14 , wherein each of said current integration circuit and said voltage integration circuit comprises an analog-to-digital converter configured to convert said current and voltage integration signals to corresponding digital signals.

16. The DC impedance detection circuit of claim 8 , further comprising:
a) a first filter circuit configured to filter said voltage of said speaker; and
b) a second filter circuit configured to filter said current of said speaker, wherein said first and second filter circuits have a same configu

Assignees

• Silergy Semiconductor Technology Hangzhou Ltd

Inventors

• Cao Hejinsheng

Classifications

• G01R19/0023

  Measuring currents or voltages from sources with high internal resistance by means of measuring circuits with high input impedance, e.g. OP-amplifiers (electrostatic instruments G01R5/28; measuring electrostatic potential G01R15/165; measuring electrostatic fields G01R29/12; amplifiers per se H03F) · CPC title

• H03F3/2173

  of the bridge type · CPC title

• H03F3/183

  with semiconductor devices only · CPC title

• H04R29/001 Primary

  for loudspeakers (H04R29/007 takes precedence) · CPC title

• H03F2200/03

  the amplifier being designed for audio applications · CPC title