Pulse width modulation (PWM) for multi-level power inverters

Patent metadata

Field	Value
Publication number	US-9716444-B2
Application number	US-201514933004-A
Country	US
Kind code	B2
Filing date	Nov 5, 2015
Priority date	Nov 5, 2015
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

Provided is a method for controlling operation of semiconductor gates in a power conversion system including one or more multilevel inverters coupleable to a modulator and a controller. The method includes generating, via the controller, a control signal responsive to an output current power factor associated with the inverters and producing a discontinuous pulse width modulation reference signal based upon the control signal and a target output power, the discontinuous pulse width modulation reference signal being indicative of shifting a phase angle between current and voltage. A gating signal is generated for output from the modulator, as a function of the reference signal and a carrier waveform. The gating signal adjusts the phase angle to prevent switching of the semiconductor gates.

First claim

What is claimed is:

1. A method for controlling operation of gates of a plurality of semiconductors in a power conversion system including one or more multilevel inverters coupleable to a modulator and a controller, the method comprising:
generating, via the controller, a control signal responsive to an output current power factor associated with the one or more multilevel inverters;
producing a discontinuous pulse width modulation reference signal based upon the control signal and a target output power, the discontinuous pulse width modulation reference signal being indicative of shifting a phase angle between current and voltage; and
generating a gating signal, for output from the modulator, as a function of the reference signal and a carrier waveform;
wherein the gating signal adjusts the phase angle to prevent switching of the gates of the plurality of semiconductors.

2. The method of claim 1 , wherein the adjusted phase angle is associated with timing of the discontinuous portion of the pulse width modulation.

3. The method of claim 1 , further comprising, aligning the output current power factor with an output voltage associated with the plurality of semiconductors.

4. The method of claim 1 , wherein the plurality of semiconductors are insulated gate bipolar transistors (IGBTs).

5. The method of claim 4 , wherein the one or more multilevel inverters are configured in a neutral point clamped (NPC) arrangement.

6. The method of claim 1 , wherein the power conversion system is constructed for three-phase operation.

7. The method of claim 1 , wherein the control signal is user programmable via the controller.

8. A computer readable media storing instructions wherein said instructions when executed are adapted to control operation of gates of a plurality of semiconductors in a power conversion system including one or more multilevel inverters coupleable to a modulator and a controller, with a method comprising:
generating, via the controller, a control signal responsive to an output current power factor associated with the one or more multilevel inverters;
producing a discontinuous pulse width modulation reference signal based upon the control signal and a target output power, the discontinuous pulse width modulation reference signal being indicative of shifting a phase angle between current and voltage; and
generating a gating signal, for output from the modulator, as a function of the reference signal and a carrier waveform;
wherein the gating signal adjusts the phase angle to prevent switching of the gates of the plurality of semiconductors.

9. The computer readable media of claim 8 , wherein the adjusted phase angle is associated with timing of the discontinuous portion of the pulse width modulation.

10. The computer readable media of claim 8 , further comprising, aligning the output current factor with an output voltage associated with the plurality of semiconductors.

11. The computer readable media of claim 8 , wherein the plurality of semiconductors are insulated gate bipolar transistors (IGBTs).

12. The computer readable media of claim 11 , wherein the one or more multilevel inverters are configured in a neutral point clamped (NPC) arrangement.

13. The computer readable media of claim 8 , wherein the power conversion system is constructed for three-phase operation.

14. The computer readable media of claim 8 , wherein the control signal is user programmable via the controller.

15. A system for controlling operation of gates of a plurality of semiconductor in a power conversion system including one or more multilevel inverters coupleable to a modulator and a controller, the system comprising:
a controller configured for producing a control signal responsive to an output current power factor associated with the one or more multilevel inverters; and
a modulator coupled to the controller and configured for producing a discontinuous pulse width modulation reference signal based upon the control signal and a target output power, the
discontinuous pulse width modulation reference signal being indicative of shifting a phase angle between current and voltage;
wherein the modulator is configured to generate a gating signal, for output from the modulator, as a function of the reference signal and a carrier waveform; and
wherein the gating signal adjusts the phase angle to prevent switching of the gates of the plurality of semiconductors.

16. The system of claim 15 , wherein the plurality of semiconductors are insulated gate bipolar transistors (IGBTs).

17. The system of claim 15 , wherein the one or more multilevel inverters are configured in a neutral point clamped (NPC) arrangement.

18. The system of claim 15 , wherein the power conversion system is constructed for three-phase operation.

19. The system of claim 15 , wherein the control signal is user programmable via a controller.

20. The system of claim 15 , wherein the gating signal controls switching of the plurality of semiconductors.

21. The system of claim 20 , wherein the plurality of semiconductors are controlled when the output current power factor is at a maximum value.

22. The method of claim 1 , wherein the plurality of semiconductors are controlled when the output current power factor is at a maximum value.

Assignees

• Ge Energy Power Conversion Technology Ltd

Inventors

• Wagoner Robert Gregory
• Luo Cheng
• Pant Siddharth

Classifications

• H02M7/537 Primary

  using semiconductor devices only, e.g. single switched pulse inverters · CPC title

• H02M1/42

  Circuits or arrangements for compensating for or adjusting power factor in converters or inverters · CPC title

• H02M7/487 Primary

  Neutral point clamped inverters · CPC title

• H02M1/327

  against abnormal temperatures · CPC title

• H02M7/5395

  by pulse-width modulation · CPC title