Solid STTE power controller with parallel MOSFET load sharing

Patent metadata

Field	Value
Publication number	US-9716385-B2
Application number	US-201414305690-A
Country	US
Kind code	B2
Filing date	Jun 16, 2014
Priority date	Jun 16, 2014
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

A solid state power control (SSPC) controls flow of current from a power bus to an inductive load. The SSPC utilizes load sharing, in which a plurality of current supply paths are connected in parallel to control and share the flow of current between the power bus and the inductive load. Each current supply path includes a main power switching field effect transistor (FET); a balance resistor, and a secondary FET. The balance resistor is connected between the main FET and the load. The secondary FET shunts the balance resistor when the main FET is turned on, and allows current flow through the balance resistor during a turn-off time of the main FET. The balance resistor modulates gate-source voltage of the main FET in order to compensate for gate-source threshold differences among the main FETs that could lead to unequal current sharing during the turn-off period.

First claim

The invention claimed is:

1. A solid state power controller (SSPC) for controlling flow of current from a power bus to a load, the SSPC comprising:
a plurality of current supply paths connected in parallel to control current flow between the power bus and the load, each current supply path comprising:
a main power switching FET;
a balance resistor connected in the current supply path in series between the main power switching FET and the load to modulate gate-to-source voltage of the main power switching FET as a function of current flowing through the balance resistor; and
a secondary FET, connected in parallel with the balance resistor, that shunts the balance resistor to prevent modulation of the source voltage of the main power switching FET when the main power switching FET and the secondary FET are turned on, and allows current flow through the balance resistor to allow modulation of the source voltage of the main power switching FET during a turn-off time of the main power switching FET, so that unbalance in current distribution among the plurality of parallel current supply paths during turn-off caused by differences in gate-to-source threshold voltage of the main power switching FETs is counteracted by the modulation of the gate-to-source voltages by the balance resistors; and

a controller that provides turn-on and turn-off signals to the main power switching FETs and the secondary FETs.

2. The SSPC of claim 1 and further comprising:
a current sensing resistor connected between the plurality of current supply paths and the load.

3. The SSPC of claim 2 , wherein the controller provides the turn-off signals as a function of current flow through the current sensing resistor.

4. The SSPC of claim 1 wherein the main power switching FETs and the secondary FETs are MOSFETs.

5. The SSPC of claim 1 wherein the balance resistor is connected to the source of the main power switching FET so that an increase in voltage across the balance resistor increases source voltage of the main power switching FET during turn-off to cause gate-to-source voltage of the main power switching FET to decrease and current flow through the main power switching FET to decrease.

6. The SSPC of claim 1 wherein each current supply path further comprises an inductor connected between the main power switching FET and the balance resistor.

7. The SSPC of claim 1 wherein the controller is configured to provide turn-on signals to gates of the main power switching FETs to cause the main power switching FETs operate in a fully ON saturated state, and is configured to provide turn-off signals to the gates of main power switching FETs to cause the main power switching FETs to operate during turn-off in a linear region with current flow through the main power switching FETs and voltage across source to drain of the main power switching FETs until energy inductively stored in the load is dissipated.

8. The SSPC of claim 1 , wherein the controller is configured to provide turn-on signals to gates of the secondary FETs that are delayed with respect to the turn-on signals provided by the controller to gates of the main power switching FETs.

9. A method of controlling current flow from a power bus to an inductive load, the method comprising;
supplying current through a plurality of parallel current supply paths from the power bus to the inductive load;
providing a turn-off signal to a main power switching FET in each of the current supply paths, each main power switching FET having a gate, a drain, and a source;
in response to the turn-off signal, introducing into each of the current supply paths, a balance resistor connected in series between the source of the main power switching FET and the load to modulate gate-to-source voltage of the main power switching FET in that current supply path as a function of current flow through the balance resistor, so that unbalance in current distribution among the parallel current supply paths during turn-off caused by differences in gate-to-source threshold voltages of the main power switching FETs is counteracted.

10. The method of claim 9 and further comprising:
shunting the balance resistor in each current supply path with a secondary FET that is turned on when the main power switching FET is turned on.

11. The method of claim 10 , wherein introducing the balance resistor comprises:
turning off the secondary FET in response to the turn-off signal.

12. The method of claim 11 and further comprising:
delaying turn-on of the secondary FET with respect to turn-on of the main power switching FET.

13. The method of claim 9 , wherein each current supply path includes an inductor between the main power switching FET and the balance resistor.

14. The method of claim 9 , wherein the main power switching FETs operate in a fully ON saturated state while supplying current though the parallel current supply paths prior to receiving the turn-off signal, and operate in a linear region after receiving the turn-off signal until energy inductively stored in the inductive load is dissipated.

15. A solid state power controller (SSPC) for controlling flow of current from a power bus to a load, the SSPC comprising:
a plurality of current supply paths connected in parallel to control current flow between the power bus and the load, each current supply path comprising:
a main power switching FET;
a balance resistor connected in the current supply path between the main power switching FET and the load;
a secondary FET that shunts the balance resistor when the main power switching FET and the secondary FET are turned on, and allows current flow through the balance resistor during a turn-off time of the main power switching FET;
a current sensing resistor connected between the plurality of current supply paths and the load; and

a controller that provides turn-on and turn-off signals to the main power switching FETs and the secondary FETs, wherein the controller provides the turn-off signals as a function of current flow through the current sensing resistor.

16. A solid state power controller (SSPC) for controlling flow of current from a power bus to a load, the SSPC comprising:
a plurality of current supply paths connected in parallel to control current flow between the power bus and the load, each current supply path comprising:
a main power switching FET;
a balance resistor connected in the current supply path between the main power switching FET and the load;
an inductor connected between the main power switching FET and the balance resistor; and
a secondary FET that shunts the balance resistor when the main power switching FET and the secondary FET are turned on, and allows current flow through the balance resistor during a turn-off time of the main power switching FET; and

a controller that provides turn-on and turn-off signals to the main power switching FETs and the secondary FETs.

17. A method of controlling current flow from a power bus to an inductive load, the method comprising;
supplying current through a plurality of parallel current supply paths from the power bus to the inductive load;
providing a turn-off signal to a main power switching FET in each of the current supply paths;
in response to the turn-off signal, introducing into each of the current supply paths, a balance resistor to modulate gate-to-source voltage of the main power switching FET in that current supply path as a function of current flow through the balance resistor, wherein introducing the balance resistor comprises turning off a secondary FET in response to the turn-off signal;
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Assignees

• Hamilton Sundstrand Corp

Inventors

• Dickey John A

Classifications

• H03K2217/0036

  Means reducing energy consumption · CPC title

• H02J4/00 Primary

  Circuit arrangements for mains or distribution networks not specified as AC or DC; Circuit arrangements for mains or distribution networks combining AC and DC sections or sub-networks (arrangements using intermediate DC-AC-DC conversion H02J1/002; arrangements using high-voltage DC [HVDC] links H02J3/36) · CPC title

• H03K17/0822 Primary

  in field-effect transistor switches · CPC title

• H03K3/01

  Details · CPC title

• H03K17/166

  Soft switching · CPC title