Organic light-emitting diode displays with reduced border area

Patent metadata

Field	Value
Publication number	US-9716248-B2
Application number	US-201615087783-A
Country	US
Kind code	B2
Filing date	Mar 31, 2016
Priority date	Dec 18, 2015
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

A display having thin-film transistor (TFT) structures may be used to display images within an active area of the display, which is surrounded by an inactive border area. In order to reduce the inactive area, a TFT passivation layer may be used to help protect conductive routing lines at the outer edge of the border so that encapsulation layers need not be formed all the way to the edge. At least some of the conductive routing lines in the inactive area may be stacked or coupled in parallel to help reduce border width. The TFT passivation layer may also cover the lateral edges of the routing lines to help prevent corrosion during an anode etch. The encapsulation layers may also be formed in a bent portion of the display substrate to help adjust the neutral stress plane such that metal traces formed in the bent portion do not crack.

First claim

What is claimed is:

1. A display having an active area and an inactive area surrounding the active area, comprising:
a substrate;
a conductive routing structure formed on the substrate in the inactive area of the display;
encapsulation layers formed over the active area of the display, wherein the encapsulation layers comprise a first inorganic layer, a second inorganic layer, and an organic layer interposed between the first and second inorganic layers;
a dam structure that contains the encapsulation layers within the display and that is formed directly over the conductive routing structure; and
a passivation layer that protects the conductive routing structure and that is formed below the encapsulation layers, the passivation layer covers an outer lateral edge of the conductive routing structure.

2. The display of claim 1 , further comprising:
an anode layer formed over the passivation layer; and
a cathode layer formed over the anode layer, wherein the anode and cathode layers form an organic light-emitting diode.

3. The display of claim 1 , wherein the dam structure is formed away from the outer edge of the conductive routing structure.

4. The display of claim 1 , further comprising:
an anode layer formed over the substrate;
a cathode layer formed over the substrate;
a first conductive structure formed below the cathode layer in the inactive area;
a second conductive structure formed directly above the first conductive structure;
a first planarization layer formed between the first and second conductive structures;
a via formed through the first planarization layer that shorts the first conductive structure to the second conductive structure; and
a second planarization layer formed between the anode layer and the second conductive structure.

5. The display of claim 4 , wherein the passivation layer is at least partially formed on the second conductive structure.

6. Display circuitry, comprising:
a substrate;
display pixels formed over the substrate in an active area, wherein the active area is surrounded by an inactive area;
a first conductor formed on the substrate in the inactive area;
a second conductor formed over the first conductor;
a first planarization layer formed between the first and second conductors;
a second planarization layer formed on the second conductor; and
a pixel definition layer formed on the second planarization layer, wherein the first conductor is shorted to the second conductor;
a third conductor formed on the substrate in the same layer as the first conductor; and
an anode layer coupled to the third conductor.

7. The display circuitry of claim 6 , wherein the first and second conductors carry a power supply voltage.

8. The display circuitry of claim 7 , further comprising:
a fourth conductor formed over the third conductor in the same layer as the second conductor, wherein the third conductor is shorted to the fourth conductor, and wherein the first and third conductors carry a different power supply voltage.

9. The display circuitry of claim 6 , further comprising:
a fourth conductor formed directly on the third conductor.

10. The display circuitry of claim 6 , further comprising:
encapsulation layers formed over the active area;
a dam structure that contains the encapsulation layers within the active area and that is formed directly over the third conductor; and
a passivation layer that is formed under the encapsulation layers and that protects the third conductor.

11. The display circuitry of claim 10 , wherein the passivation layer covers both an outer facing edge of the third conductor and lateral edges of the third conductor.

12. The display circuitry of claim 10 , wherein the encapsulation layers comprises a first inorganic layer, a second inorganic layer, and an organic polymer layer sandwiched between the first and second inorganic layers.

13. A display having an active area and an inactive area surrounding the active area, comprising:
a substrate;
a conductive routing structure formed on the substrate in the inactive area of the display;
encapsulation layers formed over the active area of the display;
a first dam structure that contains the encapsulation layers within the display and that is formed directly over the conductive routing structure;
a second dam structure that covers an outer lateral edge of the conductive routing structure; and
a third dam structure that helps contain the encapsulation layers within the display and that is physically interposed between the first and second dam structures.

14. The display of claim 13 , further comprising:
a polarizer film formed over the substrate that completely covers the encapsulation layers.

15. The display of claim 13 , further comprising:
a passivation layer that protects the conductive routing structure and that is formed below the encapsulation layers and below the first, second, and third dam structures.

Assignees

• Apple Inc

Inventors

• Visweswaran Bhadrinarayana Lalgudi
• Zhang Zhen
• Rieutort-Louis Warren S
• Tsai Tsung-Ting

Classifications

• Y02E10/549

  Organic PV cells · CPC title

• H01L27/323

  Electricity · mapped topic

• H01L2251/5315

  Electricity · mapped topic

• H01L51/5206

  Electricity · mapped topic

• H01L27/3258

  Electricity · mapped topic