Field effect transistor

US9716185B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9716185-B2
Application numberUS-201615002748-A
CountryUS
Kind codeB2
Filing dateJan 21, 2016
Priority dateApr 30, 2015
Publication dateJul 25, 2017
Grant dateJul 25, 2017

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Abstract

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A field effect transistor includes: a semiconductor substrate having a main surface; a plurality of source electrodes and a plurality of drain electrodes alternately disposed and ohmic-connected with the main surface of the semiconductor substrate; a plurality of gate electrodes Schottky-connected with the main surface of the semiconductor substrate and respectively disposed between the plurality of source electrodes and the plurality of drain electrodes; and a Schottky electrode Schottky-connected with the main surface of the semiconductor substrate, wherein each of the plurality of drain electrodes has first and second portions separated from each other, a sum of widths of the first and second portions of each drain electrode is smaller than a width of one source electrode, the Schottky electrode is disposed between the first portion and the second portion of the drain electrode.

First claim

Opening claim text (preview).

What is claimed is: 1. A field effect transistor comprising: a semiconductor substrate having a main surface; first and second source electrodes ohmic-connected with the main surface of the semiconductor substrate; a drain electrode including first and second fingers ohmic-connected with the main surface of the semiconductor substrate, wherein the first and second fingers are disposed between the first and second source electrodes; first and second gate electrodes Schottky-connected with the main surface of the semiconductor substrate wherein the first gate electrode is disposed between the first source electrode and the first finger, and the second gate electrode is disposed between the second finger and the second source electrode; and a Schottky electrode Schottky-connected with the main surface of the semiconductor substrate, wherein a sum of widths of the first and second fingers is smaller than a width of one of the first and second source electrodes, and the Schottky electrode is disposed between the first finger and the second finger, and wherein no source electrode is provided between the first and second fingers of the drain electrode. 2. The field effect transistor of claim 1 , further comprising a pad connected electrically to the Schottky electrode, wherein the Schottky electrode is not electrically connected to the first and second gate electrodes. 3. The field effect transistor of claim 1 , wherein the Schottky electrode is electrically connected to the first and second gate electrodes. 4. The field effect transistor of claim 3 , further comprising: a common pad electrically connected to the first and second gate electrodes and the Schottky electrode; a first resistor connected between the first and second gate electrodes and the common pad; and a second resistor connected between the Schottky electrode and the common pad. 5. The field effect transistor of claim 1 , further comprising an electrode layer on the drain electrode and extending over the Schottky electrode. 6. The field effect transistor of claim 1 , further comprising an electrode layer on the drain electrode and connected to the first and second fingers without contacting the semiconductor substrate and the Schottky electrode. 7. The field effect transistor of claim 1 , wherein the semiconductor substrate includes a Si substrate and a GaN-based epitaxial layer on the Si substrate. 8. The field effect transistor of claim 7 , wherein the GaN-based epitaxial layer includes an AlGaN/GaN HEMT structure. 9. The field effect transistor of claim 1 , wherein a sum of widths of the first and second fingers is smaller than a width of one of the first and second source electrodes.

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What does patent US9716185B2 cover?
A field effect transistor includes: a semiconductor substrate having a main surface; a plurality of source electrodes and a plurality of drain electrodes alternately disposed and ohmic-connected with the main surface of the semiconductor substrate; a plurality of gate electrodes Schottky-connected with the main surface of the semiconductor substrate and respectively disposed between the plurali…
Who is the assignee on this patent?
Mitsubishi Electric Corp
What technology area does this patent fall under?
Primary CPC classification H01L29/8124. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 25 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).