Silicide regions in vertical gate all around (VGAA) devices and methods of forming same

Patent metadata

Field	Value
Publication number	US-9716143-B2
Application number	US-201615194238-A
Country	US
Kind code	B2
Filing date	Jun 27, 2016
Priority date	Dec 19, 2014
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

An embodiment semiconductor device includes a nanowire extending upwards from a semiconductor substrate, a source/drain region in the nanowire, and a channel region in the nanowire over the source/drain region. The source/drain region further extends into the semiconductor substrate past edges of the nanowire. The semiconductor device further includes a gate structure encircling the channel region and a silicide in an upper portion of the source/drain region. A sidewall of the silicide is aligned with a sidewall of the gate structure.

First claim

What is claimed is:

1. A semiconductor device comprising:
a nanowire extending upwards from a semiconductor substrate;
a first source/drain region in the nanowire, wherein the first source/drain region further extends into the semiconductor substrate past edges of the nanowire; and
a channel region in the nanowire over the first source/drain region;
a gate structure encircling the channel region; and
a silicide in an upper portion of the first source/drain region, wherein the silicide extends to a sidewall of the gate structure.

2. The semiconductor device of claim 1 further comprising a shallow trench isolation (STI) region in the semiconductor substrate, wherein the silicide extends to the STI region.

3. The semiconductor device of claim 1 further comprising:
an interlayer dielectric layer (ILD) over the silicide; and
a contact extending through the ILD and electrically connected to the silicide.

4. The semiconductor device of claim 3 , wherein a first lateral dimension of the silicide is greater than a second lateral dimension of the contact.

5. The semiconductor device of claim 3 , wherein a sidewall of the silicide is closer to the nanowire than the contact.

6. The semiconductor device of claim 1 further comprising a spacer layer disposed between the first source/drain region and the gate structure.

7. The semiconductor device of claim 1 , further comprising a second source/drain region in the nanowire over the channel region.

8. The semiconductor device of claim 1 , wherein the silicide does not extend into at least a portion of the first source/drain region under the gate structure.

9. A semiconductor device comprising:
a vertical gate all around (VGAA) transistor, the transistor comprising:
a first source/drain region at a top surface of a semiconductor substrate;
a channel region over the first source/drain region;
a second source/drain region over the channel region; and
a gate structure disposed around the channel region;

a shallow trench isolation (STI) region adjacent the first source/drain region; and
a silicide region in the first source/drain region, wherein the silicide region extends laterally from the gate structure to the STI region.

10. The semiconductor device of claim 9 further comprising a dielectric layer over the top surface of the semiconductor substrate, wherein the dielectric layer extends along sidewalls of the gate structure and the second source/drain region.

11. The semiconductor device of claim 10 further comprising a source/drain contact extending through the dielectric layer and electrically connected to first source/drain region through the silicide region.

12. The semiconductor device of claim ii, wherein a lateral dimension of the silicide region is greater than a lateral dimension of the first source/drain region.

13. The semiconductor device of claim 9 , wherein the channel region, the second source/drain region, and at least a portion of the first source/drain region are disposed in a nanowire extending upwards from the semiconductor substrate.

14. The semiconductor device of claim 9 , wherein the silicide region is disposed along multiple sides of the gate structure in a top-down view of the semiconductor device.

15. The semiconductor device of claim 9 , wherein the STI region is disposed along multiple sides of the gate structure in a top-down view of the semiconductor device.

16. A device comprising:
a semiconductor substrate;
a source/drain region at a top surface of the semiconductor substrate, wherein a portion of the source/drain region extends into a nanowire;
a silicide region at a top surface of the source/drain region;
a gate structure disposed around a channel region of the nanowire, wherein the gate structure is further disposed over the portion of the source/drain region;
a dielectric layer disposed along sidewalls of the gate structure; and
a source/drain contact extending through the dielectric layer and electrically connected to the source/drain region through the silicide region, wherein a lateral distance between the silicide region and the channel region is less than a lateral distance between the source/drain contact and the channel region.

17. The device of claim 16 further comprising a shallow trench isolation (STI) region extending into the semiconductor substrate, wherein the silicide region extends to a sidewall of the STI region.

18. The device of claim 16 , wherein the silicide region extends to a line disposed along a sidewall of the gate structure.

19. The device of claim 16 , wherein the gate structure is disposed around a channel region of a plurality of nanowires.

20. The device of claim 16 , wherein the nanowire further includes an additional source/drain region over the channel region, wherein a top of the gate structure is substantially level with a bottom of the additional source/drain region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Kai-Chieh
• Lien Wai-Yi

Classifications

• H01L29/41741

  Electricity · mapped topic

• H01L29/456

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic