Package substrate and method for manufacturing package substrate

Patent metadata

Field	Value
Publication number	US-9716059-B2
Application number	US-201514840236-A
Country	US
Kind code	B2
Filing date	Aug 31, 2015
Priority date	Sep 2, 2014
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

A package substrate includes an outermost interlayer, an outermost conductive layer including first pads positioned to mount at electronic component and second pads positioned to mount another electronic component, a first conductive layer including first circuits and formed such that the outermost interlayer is on the first conductive layer and that the first circuits are connecting the first and second pads, an inner interlayer formed such that the first conductive layer is on the inner interlayer, a second conductive layer formed such that the inner interlayer is on the second conductive layer, via conductors penetrating through the outermost interlayer and including first via conductors connecting the first conductive layer and the first pads and second via conductors connecting the first conductive layer and the second pads, and third via conductors penetrating through the inner interlayer and positioned such that the first and third via conductors form stacked via conductors.

First claim

What is claimed is:

1. A package substrate, comprising:
an outermost insulating resin interlayer;
an outermost conductive layer formed on a surface of the outermost insulating resin interlayer and comprising a plurality of first pads and a plurality of second pads such that the plurality of first pads is positioned to mount a first electronic component and the plurality of second pads is positioned to mount a second electronic component;
a first conductive layer consisting of a plurality of first conductive circuits and formed such that the outermost insulating resin interlayer is formed on the first conductive layer and that the plurality of first conductive circuits is connecting the plurality of first pads and the plurality of second pads, respectively;
an inner insulating resin interlayer formed such that the first conductive layer is formed on the inner insulating resin interlayer;
a second conductive layer formed such that the inner insulating resin interlayer is formed on the second conductive layer;
a plurality of via conductors penetrating through the outermost insulating resin interlayer and comprising a plurality of first via conductors and a plurality of second via conductors such that the first via conductors are connecting the first conductive layer and the plurality of first pads and that the second via conductors are connecting the first conductive layer and the plurality of second pads; and
a plurality of third via conductors penetrating through the inner insulating resin interlayer and positioned such that the first via conductors and third via conductors form a plurality of stacked via conductors penetrating through the outermost and inner insulating resin interlayers,
wherein the plurality of second pads includes a plurality of outermost second pads positioned in an outermost row of the plurality of second pads and formed such that the plurality of outermost second pads is connected to one of a power supply circuit or a ground circuit, and the plurality of second via conductors includes a plurality of outermost second via conductors connected to the plurality of outermost second pads, and the plurality of third via conductors includes a plurality of outer third via conductors positioned such that the outermost second via conductors and outer third via conductors form a plurality of outer stacked via conductors penetrating through the outermost and inner insulating resin interlayers.

2. A package substrate according to claim 1 , wherein the plurality of third via conductors has a plurality of land portions formed on the inner insulating resin interlayer, respectively, the first conductive layer includes the plurality of first conductive circuits and the land portions of the third via conductors, and the plurality of first conductive circuits is a plurality of data transmission lines configured to transmit data between the first and second electronic components.

3. A package substrate according to claim 1 , wherein the plurality of third via conductors has a plurality of land portions formed on the inner insulating resin interlayer, respectively, the first conductive layer is consisting of the plurality of first conductive circuits and the land portions of the third via conductors, and the plurality of first conductive circuits is a plurality of data transmission lines configured to transmit data between the first and second electronic components.

4. A package substrate according to claim 1 , wherein the outermost conductive layer, the first conductive circuits and the second conductive layer form a stripline structure.

5. A package substrate according to claim 1 , wherein the first electronic component is a logic IC device, and the second electronic component is a memory device.

6. A package substrate according to claim 5 , wherein the plurality of second pads includes a plurality of pads positioned in an outermost row, and the pads positioned in an outermost row are formed to connect to one of power source and ground.

7. A package substrate according to claim 1 , wherein the first and second via conductors are formed in openings formed in the outermost insulating resin interlayer such that the openings in the outermost insulating resin interlayer has side walls having a roughness which is greater than a surface roughness of the inner insulating resin interlayer on which the first conductive layer is formed, and the third via conductors are formed in openings formed in the inner insulating resin interlayer such that the openings in the inner insulating resin interlayer has side walls having a roughness which is greater than the surface roughness of the inner insulating resin interlayer on which the first conductive layer is formed.

8. A package substrate according to claim 7 , wherein the roughness of the side walls of the openings in the outermost and inner insulating resin interlayers is in a range of 0.3 μm to 0.9 μm.

9. A package substrate according to claim 7 , wherein the surface roughness of the inner insulating resin interlayer on which the first conductive layer is formed is in a range of 0.1 μm or less.

10. A package substrate according to claim 8 , wherein the surface roughness of the inner insulating resin interlayer on which the first conductive layer is formed is in a range of 0.1 μm or less.

11. A package substrate according to claim 1 , wherein the plurality of third via conductors is positioned directly underneath the plurality of first via conductors such that the first via conductors and third via conductors form the plurality of stacked via conductors penetrating through the outermost and inner insulating resin interlayers.

12. A package substrate according to claim 11 , wherein the plurality of third via conductors has a plurality of land portions formed on the inner insulating resin interlayer, respectively, the first conductive layer includes the plurality of first conductive circuits and the land portions of the third via conductors, and the plurality of first conductive circuits is a plurality of data transmission lines configured to transmit data between the first and second electronic components.

13. A package substrate according to claim 11 , wherein the plurality of third via conductors has a plurality of land portions formed on the inner insulating resin interlayer, respectively, the first conductive layer is consisting of the plurality of first conductive circuits and the land portions of the third via conductors, and the plurality of first conductive circuits is a plurality of data transmission lines configured to transmit data between the first and second electronic components.

14. A package substrate according to claim 11 , wherein the outermost conductive layer, the first conductive circuits and the second conductive layer form a stripline structure.

15. A package substrate according to claim 11 , wherein the first electronic component is a logic IC device, and the second electronic component is a memory device.

16. A package substrate according to claim 15 , wherein the plurality of second pads includes a plurality of pads positioned in an outermost row, and the pads positioned in an outermost row are formed to connect to one of power source and ground.

17. A package substrate according to claim 11 , wherein the first and second via conductors are formed in openings formed in the outermost insulating resin interlayer such that the openings in the outermost insulating resin interlayer has side walls having a roughness which is greater than a surface roughness of the inner insulating resin interlayer on which the first conductive layer

Assignees

• Ibiden Co Ltd

Inventors

• Inagaki Yasushi
• Futonagane Osamu

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title