Interlayer dielectric structure with high aspect ratio process (HARP)

Patent metadata

Field	Value
Publication number	US-9716044-B2
Application number	US-201113212904-A
Country	US
Kind code	B2
Filing date	Aug 18, 2011
Priority date	Aug 18, 2011
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

The present disclosure provides a method of making an integrated circuit. The method includes forming a gate stack on a semiconductor substrate; forming a stressed contact etch stop layer (CESL) on the gate stack and on the semiconductor substrate; forming a first dielectric material layer on the stressed CESL using a high aspect ratio process (HARP) at a deposition temperature greater than about 440 C to drive out hydroxide (OH) group; forming a second dielectric material layer on the first dielectric material layer; etching to form contact holes in the first and second dielectric material layers; filling the contact holes with a conductive material; and performing a chemical mechanical polishing (CMP) process.

First claim

What is claimed is:

1. A method of making an integrated circuit, the method comprising:
forming a first gate stack and a second gate stack on a semiconductor substrate;
forming a first source, a first drain, a second source, and a second drain in the semiconductor substrate, wherein the first gate stack interposes the first source and the first drain and the second gate stack interposes the second source and the second drain;
forming a stressed contact etch stop layer (CESL) over the first gate stack and the second gate stack, wherein the stressed CESL is configured to provide a tensile-stressed contact etch stop layer (T-CESL) over the first gate stack and a compressive-stressed contact etch stop layer (C-CESL) over the second gate stack, wherein a hydroxide concentration of the T-CESL is greater than a hydroxide concentration of the C-CESL;
forming a first dielectric material layer on the stressed CESL using a high aspect ratio process (HARP), wherein the HARP process is tuned to reduce the hydroxide concentration of the T-CESL;
forming a second dielectric material layer on the first dielectric material layer;
etching to form contact holes in the first and second dielectric material layers;
filling the contact holes with a conductive material; and
performing a chemical mechanical polishing (CMP) process.

2. The method of claim 1 , wherein:
the semiconductor substrate includes silicon; and
the forming of the second dielectric material layer includes forming the second dielectric material layer by high density plasma chemical vapor deposition (HDPCVD) and performing another CMP process to the second dielectric material layer.

3. The method of claim 1 , wherein the forming of the stressed CESL includes:
depositing a layer that includes silicon nitride over the first gate stack and the second gate stack; and
performing an ultra-violet (UV) treatment to the layer that includes silicon nitride over the first gate stack.

4. The method of claim 1 , wherein the filling of the contact holes with a conductive material includes filling the contact holes with tungsten (W), forming tungsten plugs.

5. The method of claim 1 , wherein the first source and the first drain are n-type doped regions in the semiconductor substrate, and the second source and the second drain are p-type doped regions.

6. The method of claim 1 , wherein:
the forming of the first dielectric material layer includes forming a first silicon oxide layer; and
the forming of the second dielectric material layer includes forming a second silicon oxide layer.

7. The method of claim 1 , wherein the etching to form contact holes in the first and second dielectric material layers includes etching the first dielectric material layer, the second dielectric material layer, and the stressed CESL.

8. The method of claim 1 , wherein a temperature of the HARP process is tuned to reduce the hydroxide concentration of the T-CESL to be substantially equal to the hydroxide concentration of the C-CESL.

9. A method of making an integrated circuit, the method comprising:
forming a first gate stack and a second gate stack on a substrate, wherein the first gate stack is disposed in a first region and the second gate stack is disposed in a second region;
forming p-type source and drain (p-S/D) features in the substrate and interposed by an n-type channel underlying the first gate stack;
forming n-type source and drain (n-S/D) features in the substrate and interposed by a p-type channel underlying the second gate stack;
forming nickel silicide features on the n-S/D features and p-S/D features;
forming a compressive contact etch stop layer (C-CESL) over the first region, wherein the C-CESL is disposed on the first gate stack;
forming a tensile contact etch stop layer (T-CESL) over the second region, wherein the T-CESL is disposed on the second gate stack, and further wherein the T-CESL interfaces with the C-CESL; and
performing a high aspect ratio process (HARP) to deposit a dielectric material over the C-CESL and the T-CESL, wherein the HARP process is tuned to provide a deposition rate of the dielectric material over the T-CESL that is substantially equal to a deposition rate of the dielectric material over the C-CESL, thereby forming a first dielectric layer that has a surface roughness substantially the same over the C-CESL.

10. The method of claim 9 , after forming the first dielectric layer, further comprising:
forming a second dielectric layer on the first dielectric layer by high density plasma chemical vapor deposition (HDPCVD), filling gaps between the first and second gate stacks; and
performing a first chemical mechanical polishing (CMP) process to the second dielectric layer.

11. The method of claim 10 , further comprising:
etching through the first dielectric layer, the second dielectric layer, the T-CESL, and the C-CESL to form contact holes therein that expose the nickel silicide features;
filling the contact holes with tungsten; and
performing a second CMP process to remove excessive tungsten on the second dielectric layer, wherein the second dielectric layer is free of tungsten residue.

12. The method of claim 9 , wherein the forming of the compressive contact etch stop layer and the forming of the tensile contact etch stop layer includes:
depositing a silicon nitride layer over the first region and the second region; and
applying an ultra-violet (UV) treatment to a portion of the silicon nitride layer over the second region.

13. The method of claim 9 , wherein:
a temperature of the HARP process is set to reduce a hydroxide concentration of the T-CESL while preventing transition of the nickel silicide features to a high-resistance phase.

14. The method of claim 6 , wherein the forming of the first gate stack and the second gate stack includes forming the first gate stack and the second gate stack with a lateral distance less than 800 angstroms.

15. A method of fabricating a device, the method comprising:
receiving a substrate having a first region and a second region;
forming a contact etch stop layer (CESL) over the substrate in the first region and the second region, wherein the CESL includes a first portion having a first hydroxide concentration and a second portion having a second hydroxide concentration, wherein the first hydroxide concentration is greater than the second hydroxide concentration; and
forming a first dielectric material layer on the CESL using a high aspect ratio process (HARP), the forming of the first dielectric material layer being configured to reduce the first hydroxide concentration of the first portion.

16. The method of claim 15 , wherein a top surface of the first dielectric material layer is substantially even and free of nodule defects, the method further comprising:
forming a second dielectric material layer over the first dielectric material layer;
forming contact holes extending through the first dielectric material layer and the second dielectric material layer, the contact holes exposing a contact feature of the gate structure;
depositing a conductive material within the contact holes; and
performing a chemical mechanical polishing (CMP) process, wherein a top surface of the second dielectric material layer is free of the conductive material.

17. The method of claim 15 , wherein the forming of the first dielectric material layer includes using a deposition temperature greater than about 440° C.

18. The method of claim 15 , further comprising forming nickel silicide features over the substrate, wherein the forming of the

Assignees

• Chang Jen-Chi
• Lin Chun-Li
• Hsu Kai-Shiung
• Kuo Ming-Shiou
• Lee Wen-Long
• Leu Po-Hsiung
• Liu Ding-I
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Jen-Chi
• Lin Chun-Li
• Hsu Kai-Shiung
• Kuo Ming-Shiou
• Lee Wen-Long
• Leu Po-Hsiung
• Liu Ding-I

Classifications

• H01L21/823807 Primary

  Electricity · mapped topic

• H01L21/823871

  Electricity · mapped topic

• H01L21/823814

  Electricity · mapped topic

• H01L21/823864

  Electricity · mapped topic

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title