Systems and methods for full-order equivalent circuit approach (ECA) modeling of layered structures

Patent metadata

Field	Value
Publication number	US-9715567-B1
Application number	US-201514796427-A
Country	US
Kind code	B1
Filing date	Jul 10, 2015
Priority date	Jul 16, 2014
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

Systems and methods are provided for generating an equivalent circuit model. RLGC parameters representing a segment of a layered structure of a specified length are received. The layered structure includes two conductors (also called planes) and at least one trace or a transmission line located between the two conductors. An admittance matrix corresponding to the segment is computed based at least in part on the received RLGC parameters. One or more loading parameters representing a loading of one of the two conductors due to the trace or traces are also computed, and a segment circuit model for the segment of the layered structure based at least in part on the admittance matrix and the one or more loading parameters.

First claim

The invention claimed is:

1. A computer implemented method for generating an equivalent circuit model, the method comprising:
receiving, in one or more computer-readable storage media, resistance, inductance, conductance, or capacitance (“RLGC”) parameters of a first segment of a layered structure of a specified length, the layered structure comprising a first conductive plane, a second conductive plane, and a first trace located between the first and second conductive planes;
computing, using one or more data processors, a relationship between end currents or end voltages of the first segment based at least in part on the received RLGC parameters;
generating, using the one or more data processors, at least one loading parameter representing electromagnetic coupling between the first conductive plane and the first trace; and
generating, using the one or more data processors, a segment circuit model for the first segment of the layered structure based at least in part on the generated relationship and the at least one loading parameter.

2. The method of claim 1 , wherein at least one of the first conductive plane and the second conductive plane has a non-rectangular shape.

3. The method of claim 1 , wherein the generated relationship is characterized as an admittance matrix comprising trans-admittance values.

4. The method of claim 3 , wherein the admittance matrix comprises a zero-order admittance matrix or a first-order admittance matrix or a full-order admittance matrix.

5. The method of claim 1 , wherein the at least one loading parameter comprises an inductive loading term or a capacitive loading term.

6. The method of claim 5 , wherein the at least one loading parameter comprises a second loading term that is a capacitive loading term or an inductive loading term.

7. The method of claim 1 , wherein:
a first substrate is disposed between the first conductive plane and the first trace, and a second, different substrate is disposed between the first trace and the second conductive plane;
the at least one loading parameter comprises an inductive loading parameter and a capacitive loading parameter that is different than the inductive loading parameter.

8. The method of claim 1 , wherein:
a second trace is located between the first and second conductive planes; and
the at least one loading parameter comprises a vector loading parameter comprising a first element representing loading of the first conductive plane due to the first trace and a second element representing loading of the first conductive plane due to the second trace.

9. The method of claim 8 , wherein the second trace is substantially coplanar with the first trace.

10. The method of claim 8 , wherein the first and the second traces are located in different planes.

11. The method of claim 10 , wherein:
a first substrate is disposed between the first conductive plane and the first trace;
a second substrate is disposed between the first trace and the second trace; and
a third substrate is disposed between the second trace and the second conductive plane.

12. The method of claim 11 , wherein a composition of at least a portion of the first substrate is different than a composition of at least a portion of the second substrate.

13. The method of claim 11 , wherein a composition of at least a portion of the second substrate is different than a composition of at least a portion of the third substrate.

14. The method of claim 11 , wherein a composition of at least a portion of the first substrate is different than a composition of at least a portion of the third substrate.

15. The method of claim 1 , further comprising:
receiving in the storage media RLGC parameters of a second segment of the layered structure of the specified length; and
repeating the computing, generating, and second generating steps to obtain a segment model for the second segment.

16. The method of claim 15 , further comprising:
combining the segment models for the first and second segments to obtain a composite model of the layered structure; and
simulating behavior of circuitry comprising the layered structure, using the composite model.

17. The method of claim 16 , further comprising computing at least one of S parameters, Y parameters, and Z parameters for the circuitry.

18. A processor-implemented system for generating an equivalent circuit model, the system comprising:
one or more data processors; and
one or more non-transitory computer-readable storage media encoded with instructions for commanding the one or more data processors to execute operations including:
receiving resistance, inductance, conductance, or capacitance (“RLGC”) parameters of a first segment of a layered structure of a specified length, the layered structure comprising a first conductive plane, a second conductive plane, and a first trace located between the first and second conductive planes;
computing a relationship between end currents or end voltages of the first segment based at least in part on the received RLGC parameters;
generating at least one loading parameter representing electromagnetic coupling between the of the first conductive plane and the first trace; and
generating a segment circuit model for the first segment of the layered structure based at least in part on the generated relationship and the at least one loading parameter.

19. The system of claim 18 , wherein the instructions are adapted for commanding the one or more data processors to execute further operations including:
receiving RLGC parameters of a second segment of the layered structure of the specified length; and
repeating the computing, generating, and deriving steps to obtain a segment model for the second segment.

20. The system of claim 19 , wherein the instructions are adapted for commanding the one or more data processors to execute further operations including:
combining the segment models for the first and second segments to obtain a composite model of the layered structure; and
simulating behavior of circuitry comprising the layered structure, using the composite model.

21. A non-transitory machine-readable storage medium encoded with instructions for commanding one or more data processors to execute operations of a method for generating an equivalent circuit model, the method comprising:
receiving resistance, inductance, conductance, or capacitance (“RLGC”) parameters of a first segment of a layered structure of a specified length, the layered structure comprising a first conductive plane, a second conductive plane, and a first trace located between the first and second conductive planes;
computing a relationship between end currents or end voltages of the first segment based at least in part on the received RLGC parameters;
generating at least one loading parameter representing electromagnetic coupling between the first conductive plane and the first trace; and
generating a segment circuit model for the first segment of the layered structure based at least in part on the generated relationship and the at least one loading parameter.

22. The computer implemented method of claim 1 , wherein the relationship between end currents or end voltages corresponding to the first circuit is a data structure representing a port matrix that characterizes the relationship in terms of one or more of the RLGC parameters.

23. The computer implemented method of claim 22 , wherein the port matrix characterizes the relationship between end cu

Assignees

• Sas Ip Inc
• Ansys Inc

Inventors

• Xu Xin
• Bracken J E
• Thiel Werner

Classifications

• G06F30/367 Primary

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F30/23 Primary

  using finite element methods [FEM] or finite difference methods [FDM] · CPC title

• G06F17/5077

  Physics · mapped topic

• G06F17/5072 Primary

  Physics · mapped topic