Memory performance evaluation using address mapping information
US-2024394164-A1 · Nov 28, 2024 · US
US9715445B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9715445-B2 |
| Application number | US-201313947850-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 22, 2013 |
| Priority date | Mar 14, 2013 |
| Publication date | Jul 25, 2017 |
| Grant date | Jul 25, 2017 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A memory system or flash card may include an algorithm for identifying and accounting for the rewrite frequency of data to be written to the card. The file system partition or file type of data may be used for monitoring rewrite frequency and predicting future rewrites. A learning algorithm that monitors rewrites may be implemented in firmware for accurate and dynamic identification of file types/partitions with the most likely rewrites. The identification of rewrites may be used to sort the data into groups (e.g. hot data=likely rewritten, and cold data=not likely to be rewritten). The hot data may stay in single level cell (SLC) update blocks longer, while the cold data can be moved to MLC blocks sooner.
Opening claim text (preview).
We claim: 1. A method for dynamically controlling rewriting of data, the method comprising: utilizing a dynamic learning phase that comprises: tracking a number of rewrites for data to be written; comparing the number of rewrites for different file types and to different file system partitions; recording rewrite frequency for the different file types and for the different file system partitions based on the comparing; associating, based on the recorded rewrite frequency, each of the file types with a category based on the rewrite frequency for that file type; and associating, based on the recorded rewrite frequency, each of the file system partitions with a category based on the rewrite frequency for that file system partition; and utilizing an implementation phase that is activated when the learning phase has been utilized for a predetermined number of writes, wherein the implementation phase comprises: receiving a write request for data to be written; identifying a file type and a file system partition for the data to be written; determining a category associated with either the identified file type or the identified file system partition; and storing the data to be written in single level cell (SLC) memory if either the category for either the identified file type or the identified file system partition includes an indication of frequent rewriting. 2. The device of claim 1 wherein the SLC memory comprises one or more update blocks. 3. The device of claim 1 wherein the storing the data by the controller further comprises: moving data to be written that is associated with either a file type or a file system partition that has a low rewrite frequency to multi-level cell (MLC) memory. 4. A flash memory device comprising: a non-volatile storage having memory blocks storing data; and a controller in communication with the non-volatile storage, the controller is configured for: utilizing a dynamic learning phase that comprises: tracking a number of rewrites for data to be written; comparing the number of rewrites for different file types and to different file system partitions; recording rewrite frequency for the different file types and for the different file system partitions based on the comparing; associating, based on the recorded rewrite frequency, each of the file types with a category based on the rewrite frequency for that file type; and associating, based on the recorded rewrite frequency, each of the file system partitions with a category based on the rewrite frequency for that file system partition; and utilizing an implementation phase that is activated when the learning phase has been utilized for a predetermined number of writes, wherein the implementation phase comprises: receiving a write request for data to be written; identifying a file type and a file system partition for the data to be written; determining a category associated with either the identified file type or the identified file system partition; and storing the data to be written in single level cell (SLC) memory if either the category for either the identified file type or the identified file system partition includes an indication of frequent rewriting. 5. The device of claim 4 wherein the determined category comprises a hot category for frequently rewritten file system partitions and a cold category for rarely rewritten file system partitions. 6. The device of claim 5 wherein the storing the data further comprises: maintaining, for the hot category, the data to be written in the SLC memory; and transferring, for the cold category, the data to be written to multi-level cell (MLC) memory. 7. The device of claim 6 wherein the SLC memory comprises one or more update blocks and the hot category data is maintained in the update blocks for a longer time than the cold category data is maintained in the MLC memory. 8. The device of claim 4 wherein the storing the data by the controller further comprises: maintaining data to be written that is associated with a file system partition that has a high rewrite frequency in update blocks; and moving data to be written that is associated with a file system partition that has a low rewrite frequency to multi-level cell (MLC) memory. 9. The device of claim 4 wherein the determined category comprises three categories, the categories including most frequently rewritten data, less frequently rewritten data, and rarely rewritten data.
in block erasable memory, e.g. flash memory · CPC title
Allocation control and policies · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.