Interconnect path failover

US9715435B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9715435-B2
Application numberUS-201615164971-A
CountryUS
Kind codeB2
Filing dateMay 26, 2016
Priority dateApr 25, 2014
Publication dateJul 25, 2017
Grant dateJul 25, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

One or more techniques and/or systems are provided for interconnect failover between a primary storage controller and a secondary storage controller. The secondary storage controller may be configured as a backup or failover storage controller for the primary storage controller in the event the primary storage controller fails. Data and/or metadata describing the data (e.g., data and/or metadata stored within a write cache) may be mirrored from the primary storage controller to the secondary storage controller over one or more interconnect paths. Responsive to identifying a failover trigger for a failed interconnect path, the secondary storage controller is instructed to fence (e.g., block) I/O operations from the failed interconnect path. Streams of data and/or metadata that were affected by the failure may be instructed to transmit such data and/or metadata over one or more non-failed interconnect paths to the secondary storage controller during failover of the failed interconnect path.

First claim

Opening claim text (preview).

What is claimed is: 1. A method, comprising: identifying a failover trigger associated with a first interconnect path between a first storage controller and a second storage controller; sending a fence instruction to the second storage controller, the fence instruction instructing the second storage controller to fence I/O operations from the first interconnect path; receiving a fence acknowledgement message from the second storage controller; and performing interconnect failover for the first interconnect path utilizing a second interconnect path to transmit storage information from the first storage controller to the second storage controller, wherein the performing interconnect failover comprises: performing a data transmission to send data, associated with the storage information, over the second interconnect path; and performing a metadata transmission of metadata, describing the data, after the data transmission is complete, wherein the metadata transmission is restricted from being performed until completion of the data transmission. 2. The method of claim 1 , wherein the first interconnect path is between a first nonvolatile memory of the first storage controller and a second nonvolatile memory of the second storage controller for data mirroring. 3. The method of claim 1 , the identifying a failover trigger comprising: determining that a polling interval has expired; and polling the second storage controller to determine whether an I/O operation has completed. 4. The method of claim 1 , the fence acknowledgement message indicating that the second storage controller will not accept I/O operations from the first interconnect path during interconnect failover for the first interconnect path. 5. The method of claim 1 , the storage information comprising cached data stored by the first storage controller within a first nonvolatile memory and metadata describing the cached data. 6. The method of claim 1 , the performing interconnect failover comprising: identifying a first stream corresponding to a first logical unit of the storage information based upon the first stream corresponding to first in-flight I/O associated with the first interconnect path; and facilitating transmission of the first stream to the second storage controller over the second interconnect path. 7. The method of claim 6 , the facilitating transmission of the first stream comprising: facilitating a second data transmission of second data, associated with the first stream, over the second interconnect path. 8. The method of claim 7 , comprising: determining that the second data transmission has completed; and facilitating a second metadata transmission of second metadata over the second interconnect path, the second metadata describing the second data. 9. The method of claim 7 , the facilitating a second data transmission of second data comprising: identifying a complete set of data associated with the first stream; and performing a single transmission of the complete set of data as the second data transmission. 10. The method of claim 1 , the storage information stored within a second nonvolatile memory of the second storage controller as a data mirror of a first nonvolatile memory of the first storage controller. 11. The method of claim 6 , the performing interconnect failover comprising: identifying a second stream corresponding to a second logical unit of the storage information based upon the second stream corresponding to second in-flight I/O associated with the first interconnect path; and facilitating transmission of the second stream to the second storage controller over the second interconnect path. 12. The method of claim 6 , the performing interconnect failover comprising: identifying a stream as an unaffected stream; and facilitating continued operation of the stream. 13. The method of claim 1 , wherein the second interconnect path corresponds to a remote direct memory access stream. 14. A computing device, comprising: memory comprising machine executable code having stored thereon instructions for performing a method; and a processor coupled to the memory, the processor configured to execute the machine executable code to cause the processor to: identify a failover trigger associated with a first interconnect path between a first storage controller and a second storage controller; send a fence instruction to the second storage controller over a second interconnect path, the fence instruction instructing the second storage controller to fence I/O operations from the first interconnect path; receive a fence acknowledgement message from the second storage controller; and perform interconnect failover for the first interconnect path utilizing the second interconnect path to transmit storage information from the first storage controller to the second storage controller, wherein the performing interconnect failover comprises: performing a data transmission to send data, associated with the storage information, over the second interconnect path; and performing a metadata transmission of metadata, describing the data, after the data transmission is complete, wherein the metadata transmission is restricted from being performed until completion of the data transmission. 15. The computing device of claim 14 , wherein the machine executable code causes the processor to: identify a first stream corresponding to a first logical unit of the storage information based upon the first stream corresponding to first in-flight I/O associated with the first interconnect path; and facilitate transmission of the first stream to the second storage controller over the second interconnect path. 16. The computing device of claim 14 , wherein the machine executable code causes the processor to: facilitate a second data transmission of second data, associated with the first stream, over the second interconnect path. 17. The computing device of claim 16 , wherein the machine executable code causes the processor to: determine that the second data transmission has completed; and facilitate a second metadata transmission of second metadata over the second interconnect path, the second metadata describing the second data. 18. The computing device of claim 14 , wherein the machine executable code causes the processor to: identify a stream as an unaffected stream; and facilitate continued operation of the stream. 19. A non-transitory machine readable medium comprising instructions, for performing a method, which when executed by a machine, causes the machine to: identify a failover trigger associated with a first interconnect path between a first storage controller and a second storage controller; send a fence instruction to the second storage controller over a second interconnect path, the fence instruction instructing the second storage controller to fence I/O operations from the first interconnect path; receive a fence acknowledgement message from the second storage controller; and perform interconnect failover for the first interconnect path utilizing the second interconnect path to transmit storage information from the first storage controller to the second storage controller, wherein the performing interconnect failover comprises: performing a data transmission to send data, associated with the storage information, over the second interconnect path; and performing a metadata transmission of metadata, describing the data, after the data transmission is complete, wherein the metadata transmission is restricted from being

Assignees

Inventors

Classifications

  • to test input/output devices or peripheral units · CPC title

  • using redundant communication controllers · CPC title

  • Techniques of failing over between control units · CPC title

  • Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs (verification or detection of system hardware configuration G06F11/2247) · CPC title

  • between storage system components · CPC title

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Frequently asked questions

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What does patent US9715435B2 cover?
One or more techniques and/or systems are provided for interconnect failover between a primary storage controller and a secondary storage controller. The secondary storage controller may be configured as a backup or failover storage controller for the primary storage controller in the event the primary storage controller fails. Data and/or metadata describing the data (e.g., data and/or metadat…
Who is the assignee on this patent?
Netapp Inc
What technology area does this patent fall under?
Primary CPC classification G06F11/2005. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 25 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).