Vector find element equal instruction

Patent metadata

Field	Value
Publication number	US-9715383-B2
Application number	US-201213421448-A
Country	US
Kind code	B2
Filing date	Mar 15, 2012
Priority date	Mar 15, 2012
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

Processing of character data is facilitated. A Find Element Equal instruction is provided that compares data of multiple vectors for equality and provides an indication of equality, if equality exists. An index associated with the equal element is stored in a target vector register. Further, the same instruction, the Find Element Equal instruction, also searches a selected vector for null elements, also referred to as zero elements. A result of the instruction is dependent on whether the null search is provided, or just the compare.

First claim

What is claimed is:

1. A computer program product for executing a machine instruction in a central processing unit, the computer program product comprising:
a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising:
at least one opcode field to provide an opcode, the opcode identifying a Vector Find Element Equal operation;
an extension field to be used in designating one or more registers;
a first register field to designate a first register, the first register comprising a first operand;
a second register field to designate a second register, the second register comprising a second operand;
a third register field to designate a third register, the third register comprising a third operand; and
a mask field, the mask field comprising one or more controls to be used during execution of the machine instruction; and

executing the machine instruction, the execution comprising:
identifying the first register based on a combination of the first register field and a first portion of the extension field, identifying the second register based on a combination of the second register field and a second portion of the extension field, and identifying the third register based on a combination of the third register field and a third portion of the extension field;
searching the second operand for a zero element, wherein the searching the second operand for a zero element finds a zero element at a first byte position and the searching provides a null index set to a value that is a byte position of a sequentially-first zero element found in the search;
comparing one or more elements of the second operand with one or more elements of the third operand for equality, wherein the comparing finds an equal element at a second byte position and the comparing provides a compare index separate from the null index, the compare index being set to a value that is a byte position of a sequentially-first equal element; and
selecting between the null index and the compare index to provide a result of executing the machine instruction, the result being the null index or the compare index and being a value of a byte position of a sequentially-first zero element or equal element or a value indicating a size of the second operand, and the selecting being based on whether an equal element or zero element is found, wherein the selecting selects the lesser of the first byte position and the second byte position.

2. The computer program product of claim 1 , wherein the result is a byte index of an element, the element being a zero element or an equal element, and the method further comprises:
adjusting the result, the adjusting comprising performing at least one operation on the result to provide an adjusted result, the adjusted result comprising an index of a first byte of the element; and
storing the adjusted result in the first operand.

3. The computer program product of claim 2 , wherein the machine instruction further comprises another mask field, the another mask field including an element size control, the element size control specifying a size of elements in at least one of the first operand, the second operand, or the third operand, and wherein the size is used in the adjusting.

4. The computer program product of claim 1 , wherein the result is a value indicating a size of the second operand, and the method further comprises storing the result in the first operand.

5. The computer program product of claim 1 , wherein the mask field comprises a condition code set control, and wherein the method comprises:
determining whether the condition code set control is set; and
based on the condition code set control being set, setting a condition code for execution of the machine instruction.

6. The computer program product of claim 5 , wherein the setting the condition code comprises one of:
setting the condition code to a value indicating detection of a zero element in a lower indexed element than any equal compares; and
setting the condition code to a value indicating a matched element.

7. The computer program product of claim 1 , wherein the executing comprises determining, at runtime, a direction for the comparing, wherein the direction is one of left-to-right or right-to-left, and the determination comprises accessing by the machine instruction a direction control to determine the direction.

8. The computer program product of claim 1 , wherein the second operand and the third operand comprise N bytes, and wherein the comparing comprises comparing in parallel the N bytes of the second operand with the N bytes of the third operand, and wherein a size of an element comprises one of one byte, two bytes or four bytes.

9. The computer program product of claim 1 , wherein the value of the byte position of the zero element comprises a byte index, the byte index being an index of a first byte of the zero element.

10. The computer program product of claim 1 , wherein the value of the byte position of the equal element comprises a byte index, the byte index being an index of a byte of the equal element.

11. The computer program product of claim 1 , wherein the selecting is based on either no equal element being detected in a lower indexed element than a zero element or no zero element being detected in a lower indexed element than an equal element.

12. The computer program product of claim 1 , wherein the selecting selects a lowest index of the null index or the compare index.

13. The computer program product of claim 1 , wherein the comparing finds at least two equal elements at different byte positions, and wherein the compare index is set to the byte position, of the different byte positions, of the sequentially-first equal element of the at least two equal elements.

14. The computer program product of claim 1 , wherein the selecting is based on whether a zero element is found with a lower byte position in the second operand than any other element of the second operand found to be equal.

15. A computer system for executing a machine instruction in a central processing unit, the computer system comprising:
a memory; and
a processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising:
obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising:
at least one opcode field to provide an opcode, the opcode identifying a Vector Find Element Equal operation;
an extension field to be used in designating one or more registers;
a first register field to designate a first register, the first register comprising a first operand;
a second register field to designate a second register, the second register comprising a second operand;
a third register field to designate a third register, the third register comprising a third operand; and
a mask field, the mask field comprising one or more controls to be used during execution of the machine instruction; and

executing the machine instruction, the execution comprising:
identifying the first register based on a combination of the first register field and a first portion of the extension field, identifying the second register based on a combination of the second register fie

Assignees

• Bradbury Jonathan D
• Gschwind Michael K
• Schwarz Eric M
• Slegel Timothy J
• IBM

Inventors

• Bradbury Jonathan D
• Gschwind Michael K
• Schwarz Eric M
• Slegel Timothy J

Classifications

• G06F9/30185

  according to one or more bits in the instruction, e.g. prefix, sub-opcode · CPC title

• G06F9/4552

  Involving translation to a different instruction set architecture, e.g. just-in-time translation in a JVM · CPC title

• G06F9/30047

  Prefetch instructions; cache control instructions · CPC title

• G06F9/30021

  Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title

• G06F9/3001 Primary

  Arithmetic instructions · CPC title