Electro-magnetic interference (EMI) shielding techniques and configurations

Patent metadata

Field	Value
Publication number	US-9713255-B2
Application number	US-201414184575-A
Country	US
Kind code	B2
Filing date	Feb 19, 2014
Priority date	Feb 19, 2014
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

Embodiments of the present disclosure are directed towards electro-magnetic interference (EMI) shielding techniques and configurations. In one embodiment, an apparatus includes a first substrate, a die having interconnect structures coupled with the first substrate to route input/output (I/O) signals between the die and the first substrate and a second substrate coupled with the first substrate, wherein the die is disposed between the first substrate and the second substrate and at least one of the first substrate and the second substrate include traces configured to provide electro-magnetic interference (EMI) shielding for the die. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An apparatus comprising:
a first substrate;
a die having interconnect structures coupled with the first substrate to route input/output (I/O) signals between the die and the first substrate; and
a second substrate coupled with the first substrate, wherein the die is disposed between the first substrate and the second substrate and the first substrate and the second substrate include traces to provide electro-magnetic interference (EMI) shielding for the die, wherein the traces of the first substrate are coupled with power or ground supply, and wherein the traces of the first substrate and the traces of the second substrate are electrically coupled to form a Faraday cage around the die.

2. The apparatus of claim 1 , wherein:
the first substrate is a printed circuit board; and
the second substrate is a printed circuit board.

3. The apparatus of claim 1 , wherein:
the first substrate is rigid; and
the second substrate is a flexible substrate to bend around the die.

4. The apparatus of claim 1 , wherein:
the traces are configured in a grid arrangement; and
a distance between adjacent traces is smaller than a pre-determined wavelength of the EMI.

5. The apparatus of claim 1 , wherein the die includes one or more through-silicon vias (TSVs) configured to route power or ground between the respective power or ground supply and transistor circuitry of the die.

6. The apparatus of claim 1 , wherein the interconnect structures are first-level interconnect structures that directly attach the die to the first substrate.

7. The apparatus of claim 1 , wherein:
the die is disposed in a die package assembly; and
the die package assembly is disposed between the first substrate and the second substrate.

8. The apparatus of claim 1 , wherein the die is one of a plurality of dies coupled with the first substrate and wherein the traces are configured to provide EMI shielding for the plurality of dies.

9. A method comprising:
providing a first substrate;
coupling a die with the first substrate using interconnect structures to route input/output (I/O) signals between the die and the first substrate; and
coupling a second substrate with the first substrate such that the die is disposed between the first substrate and the second substrate, wherein at least one of the first substrate and the second substrate include traces configured to provide electro-magnetic interference (EMI) shielding for the die, wherein the traces of the first substrate are coupled with power or ground supply, and wherein the traces of the first substrate and the traces of the second substrate form a Faraday cage around the die.

10. The method of claim 9 , wherein:
providing the first substrate comprises forming a printed circuit board; and
the second substrate is a printed circuit board.

11. The method of claim 9 , wherein:
the second substrate is a flexible substrate configured to bend around the die; and
coupling the second substrate with the first substrate comprises bending the second substrate around the die and forming package-level interconnects between the second substrate and the first substrate.

12. The method of claim 9 , further comprising:
forming the second substrate.

13. The method of claim 9 , wherein:
the traces are configured in a grid arrangement; and
a distance between adjacent traces is smaller than a pre-determined wavelength of the EMI.

14. The method claim 9 , wherein coupling the die with the first substrate comprises forming first-level interconnect structures that directly attach the die to the first substrate.

15. The method of claim 9 , wherein:
the die is disposed in a die package assembly; and
coupling the die with the substrate comprises forming second-level interconnect structures that attach the die package assembly to the first substrate.

16. The method of claim 9 , wherein the die is one of a plurality of dies, the method further comprising:
coupling the plurality of dies with the first substrate, wherein the traces are configured to provide EMI shielding for the plurality of dies.

17. A computing device comprising:
a housing enclosure;
a package assembly disposed within the housing enclosure, the package assembly including
a first substrate;
a die having interconnect structures coupled with the first substrate to route input/output (I/O) signals between the die and the first substrate; and
a second substrate coupled with the first substrate, wherein the die is disposed between the first substrate and the second substrate and the first substrate and the second substrate include traces to provide

electro-magnetic interference (EMI) shielding for the die, wherein the traces of the first substrate are coupled with power or ground supply, and wherein the traces of the first substrate and the traces of the second substrate are electrically coupled to form a Faraday cage around the die.

18. The computing device of claim 17 , wherein:
the computing device is a mobile computing device including one or more of an antenna, a flexible display, a solar panel, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera.

Assignees

• Intel Corp

Inventors

• Elsherbini Adel A
• Mahajan Ravindranath
• Guzek John S
• Deshpande Nitin A

Classifications

• Y10T29/49126

  Assembling bases · CPC title

• H05K3/361

  Assembling flexible printed circuits with other printed circuits · CPC title

• H05K2201/09245

  Crossing layout · CPC title

• H05K1/0218

  by printed shielding conductors, ground planes or power plane (H05K1/0236 takes precedence) · CPC title

• H05K1/147 Primary

  at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit (H05K1/148 takes precedence) · CPC title