Packet processing match and action unit with configurable memory allocation

Patent metadata

Field	Value
Publication number	US-9712439-B2
Application number	US-201414193177-A
Country	US
Kind code	B2
Filing date	Feb 28, 2014
Priority date	Feb 28, 2013
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A packet processing block. The block comprises an input for receiving data in a packet header vector, the vector comprising data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table, and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations and according to information stored in an action table. Each of said match table and said action table comprise one or more memories selected from a pool of unit memories, wherein each memory in the pool of unit memories is configurable to operate as either a match memory or an action memory.

First claim

The invention claimed is:

1. A switch, comprising:
an input for receiving data in a packet header vector, the vector comprising data values representing information for a packet;
circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table;
circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations and according to information stored in an action table;
wherein each of said match table and said action table comprise one or more memories selected from a pool of unit memories, wherein each memory in the pool of unit memories is configurable to operate as either a match memory and only a match memory or an action memory and only an action memory;
wherein the pool of unit memories comprises an array of unit memories;
wherein either the match table or the action comprises a region of unit memories in the array of unit memories, the region consisting of a number of the unit memories in the array; and
wherein each unit memory in the region is contiguous to at least one other unit memory in the region, along at least one of a row or column in the array.

2. The switch of claim 1 and further comprising:
a logic unit for performing either a match or action operation; and
circuitry for coupling the logic unit to the region.

3. The switch of claim 2 wherein the circuitry for coupling is for coupling the logic unit to read any unit memory in a respective row of the array and any unit memory in any row above the respective row.

4. The switch of claim 2 wherein the circuitry for coupling is configured such that the logic unit may not read any unit memory in any row below the respective row.

5. The switch of claim 2 wherein the circuitry for coupling is for coupling the logic unit to write any unit memory in a respective row of the array and any unit memory in any row above the respective row.

6. The switch of claim 2 wherein the circuitry for coupling is configured such that the logic unit may not write any unit memory in any row below the respective row.

Assignees

• Texas Instruments Inc

Inventors

• Bosshart Patrick W
• Kim Hun-Seok

Classifications

• H04L45/745

  Address table lookup; Address filtering · CPC title

• H04L45/74 Primary

  Address processing for routing · CPC title

• H04L45/74591

  using content-addressable memories [CAM] · CPC title

• H04L45/7453

  using hashing · CPC title