Cascode switch for power amplifier

Patent metadata

Field	Value
Publication number	US-9712117-B2
Application number	US-201514965633-A
Country	US
Kind code	B2
Filing date	Dec 10, 2015
Priority date	Dec 30, 2014
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

Aspects of this disclosure relate to a cascode circuit electrically coupled between an amplifier configured to amplify a radio frequency (RF) signal and different loads. The cascode circuit can function as a switch to selectively provide an output from the amplifier to a number of different loads. In certain embodiments, the cascode circuit can be electrically coupled between different stages of a multi-stage power amplifier. For instance, the amplifier can be a first stage of the multi-stage power amplifier and the different loads can include different power amplifier transistors of a second stage of the multi-stage amplifier. The cascode circuit can be implemented by bipolar transistors according to certain embodiments.

First claim

What is claimed is:

1. A power amplifier system comprising:
a first power amplifier stage configured to amplify a radio frequency signal;
a second power amplifier stage including a first power amplifier transistor and a second power amplifier transistor, the first power amplifier transistor being implemented by a first transistor array having a larger physical area than a second transistor array that implements the second power amplifier transistor; and
a cascode circuit including a first cascode transistor and a second cascode transistor, the first cascode transistor configured to selectively provide an output from the first power amplifier stage to the first power amplifier transistor, and the second cascode transistor configured to selectively provide the output from the first power amplifier stage to the second power amplifier transistor.

2. The power amplifier system of claim 1 wherein the first power amplifier stage, the second power amplifier stage, and the cascode circuit are embodied on a single die.

3. The power amplifier system of claim 2 wherein the single die is formed using one of a silicon germanium bipolar transistor process or a gallium arsenide heterojunction bipolar transistor process.

4. The power amplifier system of claim 1 wherein the first cascode transistor is a first bipolar cascode transistor and the second cascode transistor is a second bipolar cascode transistor.

5. The power amplifier system of claim 4 wherein the first power amplifier stage includes a first power amplifier stage bipolar transistor having a collector that is electrically connected to an emitter of the first cascode bipolar transistor and an emitter of the second cascode bipolar transistor.

6. A power amplifier system comprising:
a first power amplifier stage including a first power amplifier stage bipolar transistor configured to amplify a radio frequency signal;
a second power amplifier stage including a first power amplifier transistor and a second power amplifier transistor;
a cascode circuit including a first bipolar cascode transistor and a second bipolar cascode transistor, the first bipolar cascode transistor configured to selectively provide an output from the first power amplifier stage to the first power amplifier transistor, the second bipolar cascode transistor configured to selectively provide the output from the first power amplifier stage to the second power amplifier transistor, and the first power amplifier stage bipolar transistor having a collector that is electrically connected to an emitter of the first cascode bipolar transistor and an emitter of the second cascode bipolar transistor; and
a feedback circuit configured to provide feedback from a collector of at least one of the first cascode bipolar transistor or the second cascode bipolar transistor to an input of the first power amplifier stage.

7. The power amplifier system of claim 5 further comprising a termination circuit electrically coupled to a base of the first cascode bipolar transistor and configured to provide a termination impedance, the termination circuit including a resistor in series with a capacitor.

8. The power amplifier system of claim 1 wherein the first power amplifier transistor is configured to receive the output of the first power amplifier stage in a high power mode and the second power amplifier transistor is configured to receive the output of the first power amplifier stage in a low power mode.

9. The power amplifier system of claim 1 wherein the first power amplifier transistor is configured to receive the output of the first power amplifier stage when the output is within a first frequency band and the second power amplifier transistor is configured to receive the output of the first power amplifier stage when the output is within a second frequency band.

10. The power amplifier system of claim 6 wherein the first power amplifier transistor is implemented by a first transistor array having a larger physical area than a second transistor array that implements the second power amplifier transistor.

11. The power amplifier system of claim 1 wherein the second power amplifier stage includes a third power amplifier transistor and the cascode circuit includes a third cascode transistor configured to selectively provide the output from the first power amplifier stage to the third power amplifier transistor.

12. A semiconductor die comprising:
a first power amplifier transistor;
a second power amplifier transistor, the first power amplifier transistor being implemented by a first transistor array having a larger physical area than a second transistor array that implements the second power amplifier transistor; and
a cascode circuit including a first cascode bipolar transistor and a second cascode bipolar transistor, the first cascode bipolar transistor configured to selectively provide a radio frequency signal to the first power amplifier transistor, and the second cascode bipolar transistor configured to selectively provide the radio frequency signal to the second power amplifier transistor.

13. The semiconductor die of claim 12 wherein an emitter of the first cascode bipolar transistor is electrically connected to an emitter of the second cascode bipolar transistor.

14. The semiconductor die of claim 13 further comprising a first stage power amplifier bipolar transistor having a collector electrically connected to the emitter of the first cascode bipolar transistor and the emitter of the second cascode bipolar transistor.

15. The semiconductor die of claim 12 wherein the cascode circuit includes silicon germanium bipolar transistors or gallium arsenide heterojunction bipolar transistors.

16. The semiconductor die of claim 12 further comprising a termination circuit electrically connected to a base of the first bipolar cascode transistor.

17. A packaged power amplifier module comprising:
a power amplifier die including a first power amplifier stage, a second power amplifier stage including a first power amplifier transistor being implemented by a first transistor array having a larger physical area than a second transistor array that implements a second power amplifier transistor, a first cascode bipolar transistor configured to selectively provide a radio frequency signal from the first power amplifier stage to the first power amplifier transistor in a first mode, and a second cascode bipolar transistor configured to selectively provide the radio frequency signal from the first power amplifier stage to the second power amplifier transistor in a second mode;
a packaging substrate on which the power amplifier die is disposed; and
an encapsulation over the packaging substrate and the power amplifier die.

18. The packaged power amplifier module of claim 17 wherein the first power amplifier transistor is a gallium arsenide heterojunction bipolar transistor.

19. The packaged power amplifier module of claim 17 further comprising a surface mounted component on the packaging substrate, the surface mounted component being in communication with the power amplifier die.

20. The packaged power amplifier module of claim 17 further comprising a wire bond providing an electrical connection from the power amplifier die to a pad on the packaging substrate.

21. The semiconductor die of claim 14 further comprising a feedback circuit configured to provide feedback from a collector of the first cascode bipolar transistor to a base of the first stage power amplifier bipolar transistor.

22.

Assignees

• Skyworks Solutions Inc

Inventors

• Searle Kenneth Michael

Classifications

• H03F3/195

  in integrated circuits · CPC title

• H03F1/0277 Primary

  Selecting one or more amplifiers from a plurality of amplifiers · CPC title

• H03F3/245

  with semiconductor devices only · CPC title

• H03F2203/21109

  An input signal being distributed by switching to a plurality of paralleled power amplifiers · CPC title

• H03F3/211

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title