Dynamic noise mitigation in integrated circuit devices using local clock buffers

Patent metadata

Field	Value
Publication number	US-9712112-B1
Application number	US-201615331403-A
Country	US
Kind code	B1
Filing date	Oct 21, 2016
Priority date	Oct 21, 2016
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

Embodiments are directed to a method of mitigating voltage noise events. The method includes detecting the presence of a voltage noise event at the integrated circuit device. Thereafter, one or more local clock buffers (LCBs) is selected for dampening. A type of dampening is selected for the LCBs. Finally, the dampening is applied to the LCB while the voltage noise event is occurring.

First claim

What is claimed is:

1. A method of mitigating voltage noise events in an integrated circuit device, the method comprising:
detecting a presence of a voltage noise event at the integrated circuit device;
selecting a local clock buffer (LCB) for dampening;
selecting a type of dampening for the LCB; and
applying the type of dampening to the LCB while the voltage noise event is occurring.

2. The method of claim 1 , further comprising removing the LCB dampening after the voltage noise event ceases.

3. The method of claim 1 , wherein detecting the presence of a noise event comprises:
using a voltage thermometer circuit to determine that a reduction in voltage exists in a region of the integrated circuit device.

4. The method of claim 1 , further comprising:
analyzing instructions being provided to the integrated circuit device;
predicting a future presence of a voltage noise event based on the analyzing; wherein:
the selecting and applying steps occur subsequent to predicting the future presence of the voltage noise event and prior to detecting the voltage noise event.

5. The method of claim 4 , wherein applying the type of dampening to the LCB occurs subsequent to detecting the voltage noise event.

6. The method of claim 1 , wherein selecting the LCB for dampening comprises:
analyzing the voltage noise event; and
consulting a look-up table to select the LCB based on the analyzing.

7. The method of claim 1 , wherein selecting the LCB for dampening comprises:
determining a clock controller where the voltage noise event is occurring; and
selecting each LCB being controlled by the clock controller.

8. The method of claim 1 , wherein selecting the type of dampening comprises:
decoupling L1 and L2 controls from the LCB to allow non-functional switching of the L1 and L2 controls; and
allowing the voltage noise event to traverse through the LCB to open a pathway for the voltage noise event to dissipate.

9. The method of claim 1 , wherein selecting the type of dampening comprises:
choosing from the selection comprising: toggling a latched scan-out and using a gated device on a scan out chain; and
using the selected dampening to open a pathway for the voltage noise event to dissipate.

10. An integrated circuit device arranged to mitigate voltage noise events, comprising:
a detector arranged to detect a presence of a voltage noise event at the integrated circuit device;
a first selector arranged to select a local clock buffer (LCB) for dampening;
a second selector arranged to select a type of dampening for the LCB; and
a dampener arranged to apply the dampening to the LCB while the voltage noise event is occurring.

11. The integrated circuit device of claim 10 , wherein the dampener is further arranged to remove the LCB dampening after the voltage noise event ceases.

12. The integrated circuit device of claim 10 , wherein the detector is arranged to:
use a voltage thermometer circuit to determine that a reduction in voltage exists in a region of the integrated circuit device.

13. The integrated circuit device of claim 10 , further comprising:
an analyzer arranged to analyze instructions being provided to the integrated circuit device;
a predictor arranged to predict a future presence of a voltage noise event based on the analyzing; wherein:
the selecting and applying steps occur subsequent to predicting the future presence of the voltage noise event and prior to detecting the voltage noise event.

14. The integrated circuit device of claim 13 , wherein the dampener is arranged to apply the dampening to the LCB subsequent to detecting the voltage noise event.

15. The integrated circuit device of claim 10 , wherein the first selector is arranged to:
analyze the voltage noise event; and
consult a look-up table to select the LCB based on the analyzing.

16. The integrated circuit device of claim 10 , wherein the first selector is arranged to:
determine a clock controller where the voltage noise event is occurring; and
select each LCB being controlled by the clock controller.

17. The integrated circuit device of claim 10 , wherein the second selector is arranged to:
decouple L1 and L2 controls from the LCB to allow non-functional switching of the L1 and L2 controls; and
allow the voltage noise event to traverse through the LCB to open a pathway for the voltage noise event to dissipate.

18. The integrated circuit device of claim 10 , wherein the second selector is arranged to:
choose from the selection comprising: toggling a latched scan-out and using a gated device on a scan out chain; and
use the selected dampening to open a pathway for the voltage noise event to dissipate.

19. A method for generating voltage noise events in an integrated circuit device comprising:
characterizing the integrated circuit device to determine regions of the integrated circuit device that are affected by each local clock buffer (LCB) in the integrated circuit device;
selecting an LCB; and
generating a voltage noise event to the selected LCB by applying control signals to the selected LCB.

20. The method of claim 19 further comprising:
performing a workload on the integrated circuit device to determine an effect of the voltage noise event.

Assignees

• IBM

Inventors

• Pedrone Miles C
• Peterson Kirk D
• Sheets Ii John E
• Turner Andrew A

Classifications

• G01R29/26

  Measuring noise figure; Measuring signal-to-noise ratio · CPC title

• H03B29/00 Primary

  Generation of noise currents and voltages {(gasfilled discharge tubes with solid cathode specially adapted as noise generators H01J17/005)} · CPC title

• H03K5/19

  Monitoring patterns of pulse trains (indicating amplitude G01R19/00; indicating frequency G01R23/00; measuring characteristics of individual pulses G01R29/02) · CPC title

• H03K5/08

  by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding (H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30) · CPC title

• H03K19/00346 Primary

  Modifications for eliminating interference or parasitic voltages or currents · CPC title