Magnetic memory device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9711716-B2
Application number	US-201615246519-A
Country	US
Kind code	B2
Filing date	Aug 24, 2016
Priority date	Sep 25, 2015
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A magnetic memory device and a method for manufacturing the magnetic memory device are disclosed. The method includes forming a first interlayer insulating layer on a substrate, forming a first conductive pattern that penetrates the first interlayer insulating layer, forming a mold insulating layer that includes first and second mold insulating layers on the first interlayer insulating layer, forming a second conductive pattern that penetrates the first and second mold insulating layers and the first interlayer insulating layer, and forming a magnetic tunnel junction pattern on the second conductive pattern. The first mold insulating layer is in contact with the first conductive pattern, and the second mold insulating layer is disposed on the first mold insulating layer.

First claim

What is claimed is:

1. A method for manufacturing a magnetic memory device, the method comprising:
forming a first interlayer insulating layer on a substrate;
forming a first conductive pattern that penetrates the first interlayer insulating layer;
forming a mold insulating layer on the first interlayer insulating layer, the mold insulating layer comprising: a first mold insulating layer in contact with the first conductive pattern; and a second mold insulating layer on the first mold insulating layer;
forming a second conductive pattern that penetrates the first and second mold insulating layers and the first interlayer insulating layer;
forming a magnetic tunnel junction pattern on the second conductive pattern;
forming a second interlayer insulating layer that covers the magnetic tunnel junction pattern on the second mold insulating layer; and
forming a third conductive pattern that penetrates the second interlayer insulating layer, the second mold insulating layer, and the first mold insulating layer to be in contact with the first conductive pattern,
wherein the first mold insulating layer is formed by a first process at a first temperature,
wherein the second mold insulating layer is formed by a second process that is different from the first process at a second temperature that is greater than the first temperature,
wherein the first temperature is about room temperature,
wherein the first conductive pattern extends from a top surface to a bottom surface of the first interlayer insulating layer, and
wherein the second conductive pattern extends from a top surface of the second mold insulating layer to the bottom surface of the first interlayer insulating layer.

2. The method of claim 1 , wherein the first process is an atomic layer deposition (ALD) process, and
wherein the second process is a chemical vapor deposition (CVD) process.

3. The method of claim 2 , wherein the second temperature has a range from about 300° C. to about 500° C.

4. The method of claim 1 , wherein the first conductive pattern and the third conductive pattern include metals that are different from each other.

5. The method of claim 4 , wherein the metal of the third conductive pattern has a lower melting point and a lower resistivity than the metal of the first conductive pattern.

6. The method of claim 5 , wherein the first conductive pattern includes tungsten, and
wherein the third conductive pattern includes copper.

7. The method of claim 5 , wherein the second conductive pattern includes a same metal as the first conductive pattern.

8. A method to form a magnetic memory device, the method comprising:
forming a lower interlayer insulating layer on a substrate;
forming at least one first conductive pattern in lower interlayer insulating layer;
forming a first mold insulating layer on the lower interlayer insulating layer, the first mold insulating layer comprising a first thin-layer characteristic;
forming a second mold insulating layer on the first mold insulating layer, the second mold insulating layer comprising a second thin-layer characteristic that is different from the first thin-layer characteristic;
forming at least one second conductive pattern that extends through the first mold insulating layer, the second mold insulating layer, the lower interlayer insulating layer to contact the substrate;
forming a first magnetic tunnel junction pattern disposed on the second mold insulating layer, the first magnetic tunnel junction pattern being electrically connected to the at least one second conductive pattern;
forming an upper interlayer insulating layer on the second mold insulating layer; and
forming at least one third conductive pattern that extends through the upper interlayer insulating layer, the second mold insulating layer and the first mold insulating layer to be electrically connected to the at least one first conductive pattern,
wherein a top surface of the at least one first conductive pattern comprises a recessed region, and
wherein the at least one third conductive pattern is in contact with the recessed region of the at least one first conductive pattern.

9. The method of claim 8 , wherein a refractive index of the first mold insulating layer is lower than a refractive index of the second mold insulating layer.

10. The method of claim 8 , wherein each of the first mold insulating layer and the second mold insulating layer comprises a compressive stress, and
wherein a magnitude of the compressive stress of the first mold insulating layer is less than a magnitude of the compressive stress of the second mold insulating layer.

11. The method of claim 8 , wherein a density of the first mold insulating layer is less than a density of the second mold insulating layer.

12. The method of claim 8 , wherein the first mold insulating layer and the second mold insulating layer comprises silicon oxide.

13. The method of claim 8 , wherein the first mold insulating layer and the second mold insulating layer comprises materials that are different from each other.

14. The method of claim 8 , wherein the at least one second conductive pattern comprises a same metal as the at least one first conductive pattern.

15. The method of claim 8 , wherein the first mold insulating layer is formed by an atomic layer deposition (ALD) process, and
wherein the second mold insulating layer is formed by a chemical vapor deposition (CVD) process.

16. The method of claim 15 , wherein the ALD process that forms first mold insulating layer is performed at about room temperature; and
wherein the CVD process that forms the second mold insulating layer is performed in a temperature range from about 300° C. to about 500° C.

Assignees

• Son Myoungsu
• Suh Kiseok
• Koh Gwanhyeob
• Nam Kyungtae
• Song Yoonjong
• Samsung Electronics Co Ltd

Inventors

• Son Myoungsu
• Suh Kiseok
• Koh Gwanhyeob
• Nam Kyungtae
• Song Yoonjong

Classifications

• H01L43/12 Primary

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• H01L27/224

  Electricity · mapped topic

• H10N50/01 Primary

  Manufacture or treatment · CPC title