Method for manufacturing an electronic device

US9711707B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9711707-B2
Application numberUS-201414161167-A
CountryUS
Kind codeB2
Filing dateJan 22, 2014
Priority dateJan 23, 2013
Publication dateJul 18, 2017
Grant dateJul 18, 2017

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  1. Title

    What the patent document calls the invention.

  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for manufacturing an electronic device includes a through electrode forming step of forming a through electrode on an insulating base substrate; an electronic element mounting step of mounting an electronic element on one surface of the base substrate; a cover body placing step of bonding a cover body accommodating the electronic element; a conductive film forming step of forming a conductive film on the other surface of the base substrate and on an end face of the through electrode exposing on the other surface; an electrode pattern forming step of forming an electrode pattern on the end face of the through electrode and on the surface of the periphery of the end face while leaving the conductive film; and an external electrode forming step of forming an external electrode by accumulating an electroless plated film on the surface of the electrode pattern by an electroless plating method.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for manufacturing an electronic device including providing an insulating base substrate having a first surface opposite a second surface; forming a through electrode in the insulating base substrate, the through electrode comprising a metal body filling a through-hole of the insulating base substrate, such that the metal body has an end face having flat surface and continuous with at least the second surface of the insulating base substrate; mounting an electronic element on the first surface of the insulating base substrate; bonding a cover body accommodating the electronic element therein to the insulating base substrate; forming a conductive film on the second surface of the insulating base substrate and on the end face of the through electrode exposed on the second surface; forming an electrode pattern by leaving a portion of the conductive film on the end face of the through electrode and on the second surface at a periphery of the end face of the through electrode; and forming an external electrode by accumulating an electroless plated film on a top surface and a side surface of the of the electrode pattern by an electroless plating method; and forming a metal film on the surface of the electroless plated film. 2. The method for manufacturing an electronic device according to claim 1 , wherein forming the external electrode is carried out after mounting the electronic element and bonding the cover body. 3. The method for manufacturing an electronic device according to claim 1 , wherein the metal body of the through electrode is composed of an iron-nickel based alloy. 4. The method for manufacturing an electronic device according to claim 1 , wherein the electroless plated film is a nickel film or a copper film. 5. The method for manufacturing an electronic device according to claim 1 , wherein the metal film is a gold thin film. 6. The method for manufacturing an electronic device according to claim 1 , wherein the electroless plated film has a thickness of from 1 μm to 10 μm.

Assignees

Inventors

Classifications

  • the interconnections being through-semiconductor vias · CPC title

  • Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

  • H10W72/00Primary

    Interconnections or connectors in packages · CPC title

  • Electricity · mapped topic

  • Assembling to base an electrical component, e.g., capacitor, etc. · CPC title

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Frequently asked questions

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What does patent US9711707B2 cover?
A method for manufacturing an electronic device includes a through electrode forming step of forming a through electrode on an insulating base substrate; an electronic element mounting step of mounting an electronic element on one surface of the base substrate; a cover body placing step of bonding a cover body accommodating the electronic element; a conductive film forming step of forming a con…
Who is the assignee on this patent?
Seiko Instr Inc
What technology area does this patent fall under?
Primary CPC classification H10W72/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 18 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).