Optoelectronic semiconductor chip

Patent metadata

Field	Value
Publication number	US-9711699-B2
Application number	US-201214240969-A
Country	US
Kind code	B2
Filing date	Jul 6, 2012
Priority date	Aug 30, 2011
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

An optoelectronic semiconductor chip includes a semiconductor layer sequence having at least one active layer. Furthermore, the semiconductor chip has a top-side contact structure on a radiation main side of the semiconductor layer sequence and an underside contact structure on an underside situated opposite to the radiation main side. Furthermore, the semiconductor chip includes at last two trenches that extend from the radiation main side towards the underside. As seen in a plan view of the radiation main side, the top-side contact structure and the underside contact structure are arranged in a manner spaced apart from one another. Likewise as seen in a plan view of the radiation main side, the trenches are located between the top-side contact structure and the underside contact structure.

First claim

The invention claimed is:

1. An optoelectronic semiconductor chip comprising:
a semiconductor layer sequence having an active layer;
a top-side contact structure on a radiation main side of the semiconductor layer sequence;
an underside contact structure on an underside of the semiconductor layer sequence opposite to the radiation main side, wherein, as seen in a plan view of the radiation main side, the top-side contact structure and the underside contact structure are spaced apart from one another in at least one region such that in a projection onto a plane in parallel with the radiation main side, the top-side contact structure and the underside contact structure do not overlap and/or contact one another in the at least one region; and
a plurality of trenches extending from the radiation main side in a direction towards the underside, wherein the trenches in the at least one region are arranged between the top-side contact structure and the underside contact structure, and wherein the underside contact structure is formed by a plurality of islands located between contact fingers.

2. The optoelectronic semiconductor chip according to claim 1 , wherein the top-side contact structure comprises:
a contact region for attaching a bond wire;
an intermediate connection extending away from the contact region and being not provided for injecting current into the semiconductor layer sequence; and
a plurality of contact fingers extending away from the intermediate connection and is provided for injecting current into the semiconductor layer sequence, and
wherein, in each case, the trenches extend along the intermediate connection and are located between two adjacent contact fingers.

3. The optoelectronic semiconductor chip according to claim 2 ,
wherein the trenches extend into a current distribution layer of the semiconductor layer sequence, and
wherein the current distribution layer is located between the active layer and the radiation main side and, as seen from the radiation main side, the trenches penetrate at least 65% of the current distribution layer.

4. The optoelectronic semiconductor chip according to claim 2 , wherein the trenches do not extend from the radiation main side to the active layer.

5. The optoelectronic semiconductor chip according to claim 1 , wherein a plurality of the islands is arranged along each contact finger.

6. The optoelectronic semiconductor chip according to claim 2 ,
wherein at least one of the trenches is located between the intermediate connection and a further one of the trenches, and
wherein the further one of the trenches extends from one of the contact fingers to a contact finger adjacent thereto.

7. The optoelectronic semiconductor chip according to claim 2 , wherein, as seen in a plan view of the radiation main side, an angle α is between a trench and an adjacent contact finger, wherein 2°≦α≦30°.

8. The optoelectronic semiconductor chip according to claim 1 , wherein a trench extends along a contact finger.

9. The optoelectronic semiconductor chip according to claim 1 , wherein, as seen in a plan view of the radiation main side, a trench is located above the underside contact structure.

10. The optoelectronic semiconductor chip according to claim 1 , wherein the trenches penetrate at least 90% of the semiconductor layer sequence.

11. The optoelectronic semiconductor chip according to claim 1 , wherein, as seen in a plan view of the radiation main side, the trenches occupy a proportion between inclusive 0.025% and 5% of a base area of the semiconductor layer sequence.

12. The optoelectronic semiconductor chip according to claim 1 , wherein, as seen in a plan view of the radiation main side, a spacing between the trenches and an intermediate connection is at most 8 μm.

13. The optoelectronic semiconductor chip according to claim 1 , wherein a minimum spacing A is between the underside contact structure and an intermediate connection and an average spacing B is between islands of the underside contact structure, and wherein 0.4≦A/B≦2.5.

14. The optoelectronic semiconductor chip according to claim 1 , wherein the radiation main side is provided with a surface roughening to improve coupling-out of light from the semiconductor layer sequence, and wherein the surface roughening extends into the trenches.

15. An optoelectronic semiconductor chip comprising:
a semiconductor layer sequence having an active layer;
a top-side contact structure on a radiation main side of the semiconductor layer sequence;
an underside contact structure on an underside of the semiconductor layer sequence opposite to the radiation main side; and
a plurality of trenches that extend from the radiation main side in a direction towards the underside,
wherein, as seen in a plan view of the radiation main side, the top-side contact structure and the underside contact structure are spaced apart from one another in at least one region of the radiation main side and the trenches in the at least one region are arranged between the top-side contact structure and the underside contact structure,
wherein the top-side contact structure has a contact region for attaching a bond wire, an intermediate connection that extends away from the contact region and is not provided for injecting current into the semiconductor layer sequence, and a plurality of contact fingers that extend away from the intermediate connection and is provided for injecting current into the semiconductor layer sequence,
wherein, in each case, the trenches extend along the intermediate connection and are located between two adjacent contact fingers, and
wherein the intermediate connection narrows in a direction away from the contact region.

Assignees

• Tångring Ivar
• Schmid Wolfgang
• Osram Opto Semiconductors Gmbh

Inventors

• Tångring Ivar
• Schmid Wolfgang

Classifications

• H10W72/536

  the connected ends being ball-shaped · CPC title

• H01L2224/48463

  Electricity · mapped topic

• H01L33/62 Primary

  Electricity · mapped topic

• H01L33/405

  Electricity · mapped topic

• H01L33/145

  Electricity · mapped topic