Sapphire substrate and method for manufacturing the same and nitride semiconductor light emitting element

Patent metadata

Field	Value
Publication number	US-9711685-B2
Application number	US-201615095937-A
Country	US
Kind code	B2
Filing date	Apr 11, 2016
Priority date	Mar 28, 2012
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A sapphire substrate provided with a plurality of projections on a principal surface on which a nitride semiconductor is grown to form a nitride semiconductor light emitting element. The projections have a substantially triangular pyramidal-shape the projections having a plurality of side surfaces and a pointed top. The side surfaces have an inclination angle of between 53° and 59° from a bottom of the projections. The side surfaces are crystal-growth-suppressed surfaces on which a growth of the nitride semiconductor is suppressed relative to a portion of the principal surface located between adjacent projections. A bottom of the projections has a substantially triangular shape having three outwardly curved arc-shaped sides, and each of the side surfaces has a substantially triangular shape having vertexes located at the top of the projection and at both ends of a respective side of the bottom of the projection.

First claim

What is claimed is:

1. A method of growing a nitride semiconductor on a sapphire substrate, the method comprising:
providing the sapphire substrate, which comprises a principal surface that includes a plurality of projections that are spaced apart from one another, wherein an entirety of an outer surface of each projection consists essentially of no more than three curved surfaces that extend from a location proximate a bottom perimeter of the projection to a pointed top of the projection;
growing the nitride semiconductor on the principal surface such that growth of the nitride semiconductor on the outer surfaces of the projections is suppressed relative to growth of the nitride semiconductor on a crystal growth surface that is located between the projections.

2. The method of claim 1 , wherein an inclination angle of each curved surface of each projection from a plane of the bottom of the projection is in a range of 53° to 59°.

3. The method of claim 1 , wherein the bottom perimeter of each projection has a substantially polygonal shape having no more than three outwardly curved arc-shaped sides.

4. The method of claim 3 , wherein each curved surface has a substantially triangular shape of which vertexes are both ends of a side of the bottom perimeter and the pointed top of the projection.

5. The method of claim 1 , wherein the bottom of each projection has a substantially triangular shape.

6. The method of claim 1 , wherein the projections have a height in a range of 1.0 to 1.7 μm.

7. The method of claim 1 , wherein the projections are arranged periodically on the principal surface of the sapphire substrate.

8. The method of claim 1 , wherein the projections are arranged on each vertex of triangular lattice.

9. The method of claim 1 , wherein the projections are arranged on each vertex of tetragonal lattice.

10. The method of claim 1 , wherein the projections are arranged on each vertex of hexagonal lattice.

11. The method of claim 1 , wherein a distance between tops of the adjacent projections is in a range of 2.2 μm to 3.1 μm.

12. The method of claim 1 , wherein a distance between tops of the adjacent projections is in a range of 2.8 μm to 3.1 μm.

13. The method of claim 1 , wherein a ratio of an area of the crystal growth surface to that of the principal surface is in a range of 25% to 60%.

14. The method of claim 1 , wherein a ratio of an area of the crystal growth surface to that of the principal surface is in a range of 30% and 45%.

15. The method of claim 1 ,
wherein the step of growing the nitride semiconductor comprises:
growing a base layer,
growing a first conductive layer on the base layer,
growing an active layer on the first conductive layer, and
growing a second conductive layer on the active layer.

16. The method of claim 15 , wherein the first conductive layer comprises at least one Si-doped GaN layer.

17. The method of claim 16 , wherein the first conductive layer further comprises a multilayer film comprising alternating layers of undoped In 0.1 Ga 0.9 N and layers of undoped GaN.

18. The method of claim 15 , wherein the active layer comprises a multilayer film comprising alternating layers of undoped In 0.1 Ga 0.9 N and layers of undoped GaN.

19. The method of claim 15 , wherein the second conductive layer comprises a multilayer film comprising alternating layer of Mg-doped Al 0.15 Ga 0.85 N and layers of Mg-doped In 0.03 Ga 0.97 N.

Assignees

• Nichia Corp

Inventors

• Sako Naoya
• Ohara Takashi
• Inoue Yoshiki
• Shibutani Yuki
• Kawauchi Yoshihito
• Takeichi Kazuyuki
• Nagahama Yasunori

Classifications

• H10P90/00

  Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• C30B33/10

  in solutions or melts · CPC title

• C30B33/12

  in gas atmosphere or plasma · CPC title

• C30B33/08

  Etching · CPC title