Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9711651-B2
Application number	US-201514849928-A
Country	US
Kind code	B2
Filing date	Sep 10, 2015
Priority date	Dec 26, 2008
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A semiconductor device which includes a thin film transistor having an oxide semiconductor layer and excellent electrical characteristics is provided. Further, a method for manufacturing a semiconductor device in which plural kinds of thin film transistors of different structures are formed over one substrate to form plural kinds of circuits and in which the number of steps is not greatly increased is provided. After a metal thin film is formed over an insulating surface, an oxide semiconductor layer is formed thereover. Then, oxidation treatment such as heat treatment is performed to oxidize the metal thin film partly or entirely. Further, structures of thin film transistors are different between a circuit in which emphasis is placed on the speed of operation, such as a logic circuit, and a matrix circuit.

First claim

What is claimed is:

1. A semiconductor device comprising an inverter circuit and
a pixel, the inverter circuit comprising:
a first transistor; and
a second transistor,

wherein a source of the first transistor is electrically connected to a drain of the second transistor;
wherein a gate of the first transistor is electrically connected to the source of the first transistor,
wherein a channel formation region of at least one of the first transistor and the second transistor comprises a first oxide semiconductor layer and a second oxide semiconductor layer, the second oxide semiconductor layer comprising indium and zinc,
wherein the second oxide semiconductor layer is provided on the first oxide semiconductor layer, and
wherein the first oxide semiconductor layer has a lower resistivity than the second oxide semiconductor layer, and
the pixel comprising a third transistor,
wherein a channel formation region of the third transistor is formed of a single layer of a third oxide semiconductor layer.

2. The semiconductor device according to claim 1 wherein each of the first transistor and the second transistor is a bottom-gate n-channel transistor.

3. The semiconductor device according to claim 1 wherein each of the first transistor and the second transistor comprises a source electrode and a drain electrode formed over the second oxide semiconductor layer.

4. The semiconductor device according to claim 1 wherein the first transistor is a depletion transistor and the second transistor is an enhancement transistor.

5. The semiconductor device according to claim 1 wherein the second oxide semiconductor layer further comprises gallium.

6. A semiconductor device comprising an inverter circuit and a pixel,
the inverter circuit comprising:
a first transistor; and
a second transistor,

wherein a source of the first transistor is electrically connected to a drain of the second transistor;
wherein a gate of the first transistor is electrically connected to a drain of the first transistor,
wherein a channel formation region of at least one of the first transistor and the second transistor comprises a first oxide semiconductor layer and a second oxide semiconductor layer, the second oxide semiconductor layer comprising indium and zinc,
wherein the second oxide semiconductor layer is provided on the first oxide semiconductor layer, and
wherein the first oxide semiconductor layer has a lower resistivity than the second oxide semiconductor layer, and
the pixel comprising a third transistor,
wherein a channel formation region of the third transistor is formed of a single layer of a third oxide semiconductor layer.

7. The semiconductor device according to claim 6 wherein each of the first transistor and the second transistor is a bottom-gate n-channel transistor.

8. The semiconductor device according to claim 6 wherein each of the first transistor and the second transistor comprises a source electrode and a drain electrode formed over the second oxide semiconductor layer.

9. The semiconductor device according to claim 6 wherein each of the first transistor and the second transistor is an enhancement transistor.

10. The semiconductor device according to claim 6 wherein the second oxide semiconductor layer further comprises gallium.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Sakata Junichiro
• Koyama Jun

Classifications

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/3426

  Oxides · CPC title

• H10P14/22

  using physical deposition, e.g. vacuum deposition or sputtering · CPC title

• H01L29/24

  Electricity · mapped topic

• H01L29/7869 Primary

  Electricity · mapped topic