Loading effect reduction through multiple coat-etch processes

Patent metadata

Field	Value
Publication number	US-9711604-B1
Application number	US-201615079436-A
Country	US
Kind code	B1
Filing date	Mar 24, 2016
Priority date	Dec 31, 2015
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
forming a first trench, a second trench, and a third trench in a layer over a substrate, the third trench having a greater lateral dimension than the first trench and the second trench;
partially filling the first, second, and third trenches with a first conductive material;
coating a first anti-reflective material over the first, second, and third trenches that are partially filled with the first conductive material, the first anti-reflective material having a first surface topography variation;
performing a first etch-back process to partially remove the first anti-reflective material;
coating a second anti-reflective material over the first anti-reflective material, the second anti-reflective material having a second surface topography variation that is smaller than the first surface topography variation;
performing a second etch-back process to at least partially remove the second anti-reflective material in the first and second trenches; and
partially removing the first conductive material in the first and second trenches.

2. The method of claim 1 , wherein the forming of the first, second, and third trenches is performed such that the lateral dimension of the third trench is at least three times greater than a lateral dimension of the first or a lateral dimension of the second trench.

3. The method of claim 2 , wherein the forming of the first, second, and third trenches is performed such that the lateral dimension of the first trench is substantially equal to the lateral dimension of the second trench.

4. The method of claim 1 , wherein the coating of the first anti-reflective material is performed such that the first surface topography variation is caused by a loading effect, and wherein according to the first topography variation:
a first portion of the first anti-reflective material disposed over the first trench is taller than a second portion of the first anti-reflective material disposed over the second trench; and
the second portion of the first anti-reflective material is taller than a third portion of the first anti-reflective material disposed over the third trench.

5. The method of claim 1 , wherein the coating of the second anti-reflective material is performed such that the second anti-reflective material has a same material composition as the first anti-reflective material.

6. The method of claim 1 , further comprising, before the performing of the second etch-back process, forming a photoresist to cover a portion of the second anti-reflective material disposed over the third trench, and wherein the performing of the second etch-back process comprises removing portions of the second anti-reflective material not covered by the photoresist.

7. The method of claim 1 , wherein the partially removing the first conductive material is performed such that, after the partially removing:
a first portion of the first conductive material disposed in the first trench has a first height;
a second portion of the first conductive material disposed in the second trench has second first height; and
a difference between the first height and the second height is within a certain percentage of the first height or the second height.

8. The method of claim 1 , further comprising, after the first conductive material is partially removed:
completely removing the second anti-reflective material; and
completely filling the first, second, and third trenches with a second conductive material.

9. The method of claim 8 , wherein:
the partially filling the first, second, and third trenches comprises filling the first, second, and third trenches with a work function metal as the first conductive material, the work function metal being configured to tune a work function for a gate of a transistor; and
the completely filling the first, second, and third trenches comprises filling the first, second, and third trenches with a fill metal as the second conductive material, the fill metal serving as a main conductive portion of the gate of the transistor.

10. The method of claim 1 , further comprising, before the forming the first, second, and third trenches: forming a first dummy gate, a second dummy gate, and a third dummy gate, wherein the first, second, and third trenches are formed by removing the first, second, and third dummy gates, respectively.

11. A method of fabricating a semiconductor device, comprising:
forming a first opening, a second opening, and a third opening in a dielectric layer over a substrate, the first, second, and third openings having first, second, and third widths, respectively, the third width being at least three times wider than the first width or the second width;
partially filling the first, second, and third openings with a work function metal, the work function metal being configured to tune a work function of a gate of a transistor;
forming a bottom anti-reflecting coating (BARC) material over the work function metal in the first, second, and third openings, wherein a first height difference exists between a first portion of the BARC material disposed over the first opening and a second portion of the BARC material disposed over the second opening;
performing a first etch-back process to partially remove the BARC material;
forming additional BARC material on the etched-back BARC material, wherein a second height difference exists between a first portion of the additional BARC material disposed over the first opening and a second portion of the additional BARC material disposed over the second opening, wherein the second height difference is smaller than the first height difference;
forming a photoresist material over a third portion of the additional BARC material over the third opening;
performing a second etch-back process to the first and second portions of the additional BARC material, the photoresist material serving as a mask during the second etch-back process; and
thereafter partially removing the work function metal in the first and second openings, wherein after the partially removing, the work function metal disposed in the first opening and the work function metal disposed in the second opening have a height difference that is no greater than the second height difference.

12. The method of claim 11 , wherein the forming of the first, second, and third openings is performed such that the first width is equal to the second width.

13. The method of claim 11 , wherein additional BARC material and the BARC material have identical material compositions.

14. The method of claim 11 , further comprising:
completely removing the BARC material; and
completely filling the first, second, and third openings with a metal material different from the work function metal.

15. The method of claim 11 , further comprising, before the forming the first, second, and third openings: forming a first dummy gate, a second dummy gate, and a third dummy gate, wherein the first, second, and third openings are formed by removing the first, second, and third dummy gates, respectively.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Jin-Dah
• Shieh Ming-Feng
• Wu Han-Wei
• Lin Yu-Hsien
• Liu Po-Chun
• Chen Stan

Classifications

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10W10/20

  Air gaps · CPC title

• H10W10/021

  of air gaps · CPC title

• H10P14/40 Primary

  of conductive or resistive materials · CPC title