Display device

US9711583B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9711583-B2
Application numberUS-201414558434-A
CountryUS
Kind codeB2
Filing dateDec 2, 2014
Priority dateJul 17, 2014
Publication dateJul 18, 2017
Grant dateJul 18, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Discussed is a display device, that may include a substrate divided into a display area and a non-display area except the display area, a first light shielding film formed in the display area, a second light shielding film formed in the non-display area, and oxide thin film transistors and organic light emitting diodes, which are formed on the first light shielding film, wherein the first light shielding film and the second light shielding film are spaced apart from each other.

First claim

Opening claim text (preview).

What is claimed is: 1. A display device, comprising: a substrate divided into a display area and a non-display area surrounding the display area, wherein the display area includes a thin film transistor (TFT) including an active layer, a gate electrode, and source and drain electrodes; a first light shielding film formed in the display area, the first light shielding film being disposed under the active layer of the TFT throughout the display area; and a second light shielding film formed in the non-display area, wherein the second light shielding film is positioned in a partial region of the non-display area to surround an edge of the non-display area such that the first and second light shielding films are spaced apart from each other in the non-display area. 2. The display device of claim 1 , wherein the first light shielding film is formed in an entire region of the display area and is further formed in an edge region of the non-display area. 3. The display device of claim 1 , wherein the second light shielding film surrounds an edge of the substrate. 4. The display device of claim 3 , wherein the second light shielding film is continuously or discontinuously formed. 5. The display device of claim 1 , wherein the spaced distance between the first light shielding film and the second light shielding film is 1 μm to 10,000 μm. 6. The display device of claim 1 , wherein a width of the second shielding film is 1 μm to 10,000 μm. 7. A display device, comprising: a substrate including a display area and a non-display area surrounding the display area, wherein the display area includes a thin film transistor (TFT) including an active layer formed of an oxide thin film; a first light shielding film disposed under the active layer of the TFT throughout the display area; and a second light shielding film disposed in a partial region of the non-display area to surround an edge of the non-display area such that the first and second light shielding films are spaced apart from each other in the non-display area. 8. The display device of claim 7 , wherein the first light shielding film and the second light shielding film are spaced apart from each other along a scribing line in the non-display area. 9. The display device of claim 7 , wherein the first light shielding film is formed in an entire region of the display area and is further formed in an edge region of the non-display area. 10. The display device of claim 7 , wherein the second light shielding film surrounds an edge of the substrate. 11. A method for forming a display device, the method comprising: providing a substrate including a display area and a non-display area surrounding the display area; forming a first light shielding film in the display area and a second light shielding film in the non-display area, respectively; and forming a plurality of thin film transistors (TFTs) on the first light shielding film, each TFT including an active layer, wherein the first light shielding film is formed throughout the display area to prevent light from entering the active layer of the TFT, and wherein the second light shielding film is formed in a partial region of the non-display area to surround an edge of the non-display area such that the first and second light shielding films are spaced apart from each other in the non-display area. 12. The method of claim 11 , wherein the forming the plurality of TFTs includes forming an oxide thin film on the substrate to provide the active layer of the TFT. 13. The method of claim 11 , wherein the first and second light shielding films are formed to be spaced apart from each other along a scribing line in the non-display area. 14. The method of claim 11 , wherein the forming the first light shielding film includes forming the first light shielding film in an entire region of the display area and in an edge region of the non-display area. 15. The method of claim 11 , wherein the forming the second light shielding film includes forming the second light shielding film along an edge of the substrate.

Assignees

Inventors

Classifications

  • wherein the TFTs are in active matrices · CPC title

  • comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

  • Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

  • having light shields · CPC title

  • H10K59/126Primary

    Shielding, e.g. light-blocking means over the TFTs · CPC title

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Frequently asked questions

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What does patent US9711583B2 cover?
Discussed is a display device, that may include a substrate divided into a display area and a non-display area except the display area, a first light shielding film formed in the display area, a second light shielding film formed in the non-display area, and oxide thin film transistors and organic light emitting diodes, which are formed on the first light shielding film, wherein the first light…
Who is the assignee on this patent?
Lg Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D30/6723. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 18 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 10 related publications on this page (citations in our corpus or others sharing the same primary CPC).