Method for fabricating display panel

Patent metadata

Field	Value
Publication number	US-9711542-B2
Application number	US-201414552432-A
Country	US
Kind code	B2
Filing date	Nov 24, 2014
Priority date	Jun 17, 2014
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A method for fabricating a display panel includes forming a first patterned conductive layer, a gate insulation layer, a semiconductor channel layer, a first passivation layer, a second patterned conductive layer and a pixel electrode on a first substrate. The first patterned conductive layer includes a gate electrode, and the second patterned conductive layer includes a source electrode, a drain electrode and a data line. The patterns of the gate insulation layer, the first passivation layer and the second patterned conductive layer are defined by an etching process and a lift-off process with the same photomask.

First claim

What is claimed is:

1. A method for fabricating a display panel, comprising:
forming a first patterned conductive layer on a first substrate, wherein the first patterned conductive layer comprises a first gate electrode;
forming a gate insulation layer on the first substrate and the first patterned conductive layer;
forming a semiconductor channel layer on the gate insulation layer, wherein the semiconductor channel layer overlaps the first gate electrode in a vertical projective direction;
forming a first passivation layer on the gate insulation layer and the semiconductor channel layer;
forming a patterned photoresist layer on the first passivation layer, wherein the patterned photoresist layer comprises a first photoresist pattern, a second photoresist pattern, and a plurality of openings, and a thickness of the first photoresist pattern is higher than a thickness of the second photoresist pattern;
removing the first passivation layer exposed by the openings to expose a first contact section and a second contact section of the semiconductor channel layer;
performing an ashing process to remove the second photoresist pattern and partially exposing an upper surface of the first passivation layer;
forming a conductive layer on the patterned photoresist layer, wherein the conductive layer contacts the first contact section and the second contact section, and the conductive layer contacts the upper surface of the first passivation layer exposed by the patterned photoresist layer;
performing a lift-off process to remove the patterned photoresist layer and the conductive layer on the patterned photoresist layer to form a second patterned conductive layer including a source electrode contacting the first contact section, a drain electrode contacting the second contact section, and a data line disposed on the upper surface of the first passivation layer and connected to the source electrode;
forming a second passivation layer on the second patterned conductive layer; and
forming a pixel electrode on the second passivation layer, wherein the pixel electrode is electrically connected to the drain electrode.

2. The method for fabricating the display panel of claim 1 , wherein the patterned photoresist layer on the first passivation layer is formed by:
forming a photoresist layer on the first passivation layer;
disposing a gray tone photomask above the photoresist layer, wherein the gray tone photomask has a light transmitting region, a half-tone region, and a light shielding region; and
forming the patterned photoresist layer by performing an exposure process using the gray tone photomask as a shielding mask and a developing process, wherein the light transmitting region is located corresponding to the openings, the light shielding region is located corresponding to the first photoresist pattern, and the half-tone region is located corresponding to the second photoresist pattern.

3. The method for fabricating the display panel of claim 1 , wherein the first patterned conductive layer further comprises a common line, the method further comprises removing the first passivation layer and the gate insulation layer exposed by the openings of the patterned photoresist layer to partially expose the common line, and the second patterned conductive layer further comprises a connection electrode contacting the common line exposed by the patterned photoresist layer.

4. The method for fabricating the display panel of claim 3 , further comprising:
forming a third passivation layer on the second passivation layer, wherein the third passivation layer comprises a first hole partially exposing the second passivation layer corresponding to the drain electrode and a second hole partially exposing the second passivation layer corresponding to the common line;
forming a third patterned conductive layer on the third passivation layer, wherein the third patterned conductive layer comprises a common electrode;
forming a fourth passivation layer on the third passivation layer, the third patterned conductive layer, and the second passivation layer exposed by the first hole and the second hole;
removing the fourth passivation layer and the second passivation layer in the first hole for forming a first contact hole partially exposing the drain electrode, removing a portion of the fourth passivation layer and a portion of the second passivation layer in the second hole to form a second contact hole partially exposing the common line, and a third contact hole in the fourth passivation layer partially exposing the common electrode; and
forming a fourth patterned conductive layer on the fourth passivation layer, wherein the fourth patterned conductive layer comprises the pixel electrode and a bridge electrode, the pixel electrode contacts the drain electrode via the first contact hole, the bridge electrode contacts the connection electrode via the second contact hole, and the bridge electrode contacts the common electrode via the third contact hole.

5. The method for fabricating the display panel of claim 1 , wherein a material of the second patterned conductive layer comprises a metal material.

6. The method for fabricating the display panel of claim 1 , wherein a material of the second patterned conductive layer comprises indium tin oxide (ITO) or indium zinc oxide (IZO), and the method further comprises forming a patterned auxiliary conductive layer on the second patterned conductive layer before forming the second passivation layer, wherein a pattern of the second patterned conductive layer is different from a pattern of the patterned auxiliary conductive layer, and a sheet resistance of the patterned auxiliary conductive layer is lower than a sheet resistance of the second patterned conductive layer.

7. The method for fabricating the display panel of claim 1 , wherein the second patterned conductive layer comprises a patterned transparent conductive layer and a patterned opaque conductive layer stacked with each other.

8. The method for fabricating the display panel of claim 1 , wherein the semiconductor channel layer comprises an oxide semiconductor channel layer.

9. The method for fabricating the display panel of claim 1 , further comprising:
providing a second substrate; and
forming a display medium layer between the first substrate and the second substrate.

Assignees

• Au Optronics Corp

Inventors

• Huang Yu-Han
• Huang Kuo-Yu

Classifications

• G02F1/134363

  for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS] · CPC title

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• H01L27/1288

  Electricity · mapped topic

• H01L27/124

  Electricity · mapped topic

• H01L27/1225

  Electricity · mapped topic