Package arrangement including external block comprising semiconductor material and electrically conductive plastic material

Patent metadata

Field	Value
Publication number	US-9711462-B2
Application number	US-201313889370-A
Country	US
Kind code	B2
Filing date	May 8, 2013
Priority date	May 8, 2013
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

In various embodiments, a package arrangement may be provided. The package arrangement may include at least one chip. The package arrangement may further include encapsulation material at least partially encapsulating the chip. The package arrangement may also include a redistribution structure over a first side of the chip. The package arrangement may further include a metal structure over a second side of the chip. The second side may be opposite the first side. The package arrangement may additionally include at least one of a semiconductor structure and an electrically conductive plastic material structure electrically coupled to the redistribution structure and the metal structure to form a current path between the redistribution structure and the metal structure.

First claim

What is claimed is:

1. A package arrangement, comprising:
at least one chip;
encapsulation material at least partially encapsulating the chip;
a redistribution structure over a first side of the chip;
a metal structure over a second side of the chip, wherein the second side is opposite the first side; and
a semiconductor structure electrically coupled to the redistribution structure and the metal structure;
wherein semiconductor material of the semiconductor structure forms a current path between the redistribution structure and the metal structure;
wherein the semiconductor structure comprises at least one block external from the chip, wherein the at least one block comprises the semiconductor material and wherein the at least one block further comprises electrically conductive plastic material;
wherein the at least one block is configured to be diced or sawn; and
wherein the at least one block is arranged at least partially along the perimeter of the package arrangement.

2. The package arrangement of claim 1
wherein the redistribution structure comprises a multi-layer structure.

3. The package arrangement of claim 2 ,
wherein the multi-layer structure comprises a laminate.

4. The package arrangement of claim 3 ,
wherein the multi-layer structure comprises a thin-film multi-layer structure.

5. The package arrangement of claim 1 ,
wherein the redistribution structure is coupled to a reference potential.

6. The package arrangement of claim 1 ,
wherein the metal structure is configured as a radio frequency shielding structure.

7. The package arrangement of claim 1 ,
wherein the metal structure covers the entire second side of the package arrangement.

8. The package arrangement of claim 1 ,
wherein the semiconductor structure is solar grade silicon.

9. The package arrangement of claim 1 ,
wherein the semiconductor structure is a polycrystalline silicon.

10. The package arrangement of claim 1 ,
wherein the semiconductor structure is formed by bulk semiconductor material.

11. The package arrangement of claim 1 ,
wherein semiconductor structure is in physical contact with at least one of the redistribution structure and the metal structure.

12. The package arrangement of claim 1 ,
wherein the at least one block provides an electrically conductive connection to the metal structure and a reference potential.

13. The package arrangement of claim 1 ,
wherein the at least one block is arranged next to the chip.

14. The package arrangement of claim 1 ,
wherein the at least one block is at least partially arranged in an edge region of the package arrangement.

15. The package arrangement of claim 14 ,
wherein the at least one block is at least partially arranged in a corner region of the package arrangement.

16. The package arrangement of claim 1 ,
wherein the at least one block comprises a plurality of blocks.

17. The package arrangement of claim 16 ,
wherein the blocks of the plurality of blocks are arranged in respective corner regions of the package arrangement.

18. The package arrangement of claim 1 ,
wherein the semiconductor structure comprises silicon.

19. The package arrangement of claim 18 ,
wherein the silicon comprises silicon selected from a group consisting of:
monocrystalline silicon;
polycrystalline silicon; and
amorphous silicon.

20. The package arrangement of claim 1 ,
wherein the at least one chip comprises a plurality of chips;
wherein the encapsulation material at least partially encapsulates the plurality of chips; and
wherein the block is shared by the plurality of chips to form a plurality of current path for a respective chip.

21. A package arrangement, comprising:
at least one chip, at least one bulk semiconductor piece at a package corner at least partially along the perimeter of the package arrangement, wherein the at least one bulk semiconductor piece further comprises electrically conductive plastic material;
encapsulation material at least partially encapsulating the chip and bulk semiconductor piece;
a redistribution structure over a first side of the chip and connected to the bulk semiconductor piece; and
a metal structure over a second side of the chip, connected to the bulk semiconductor piece,
wherein the second side is opposite the first side.

22. The package arrangement of claim 1 ,
wherein the chip at least partially extends throughout an entire thickness of the package arrangement.

23. A package arrangement, comprising:
at least one chip;
encapsulation material at least partially encapsulating the chip;
a redistribution structure over a first side of the chip;
a metal structure over a second side of the chip, wherein the second side is opposite the first side; and
an electrically conductive plastic material structure electrically coupled to the redistribution structure and the metal structure;
wherein electrically conductive plastic material of the electrically conductive plastic material structure forms a current path between the redistribution structure and the metal structure;
wherein the electrically conductive plastic material structure comprises at least one block external from the chip, wherein the at least one block comprises the electrically conductive plastic material;
wherein the at least one block is configured to be diced or sawn; and
wherein the at least one block is arranged at least partially along the perimeter of the package arrangement.

24. The package arrangement of claim 23 ,
wherein the electrically conductive plastic material comprises a structure selected from the group consisting of:
a polyalkene,
a polyaromatic compound comprising a double bond,
and combinations thereof.

25. The package arrangement of claim 23 ,
wherein the electrically conductive plastic material further comprises:
carbon black.

Assignees

• Infineon Technologies Ag

Inventors

• Beer Gottfried
• Maier Dominic
• Wachter Ulrich
• Kehrer Daniel

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/114 Primary

  by a substrate and the encapsulations · CPC title

• H10W74/01

  Manufacture or treatment · CPC title