Method of forming an air gap semiconductor structure with selective cap bilayer

Patent metadata

Field	Value
Publication number	US-9711455-B2
Application number	US-201514961966-A
Country	US
Kind code	B2
Filing date	Dec 8, 2015
Priority date	Nov 10, 2014
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A semiconductor substrate including one or more conductors is provided. A first layer and a second layer are deposited on the top surface of the conductors. A dielectric cap layer is formed over the semiconductor substrate and air gaps are etched into the dielectric layer. The result is a bilayer cap air gap structure with effective electrical performance.

First claim

What is claimed is:

1. A method for forming a semiconductor air gap structure, the method comprising:
providing a semiconductor substrate with one or more conductors within a dielectric layer, wherein the one or more conductors have a top surface;
depositing a first layer on the top surface of the one or more conductors;
modifying the first layer, wherein modifying the first layer comprises one or more of:
a thermal process using reactive gases, wherein timing of exposure to the reactive gases is controlled;
a direct plasma process using the reactive gases, wherein timing of the direct plasma process using the reactive gases is controlled; and
introducing the reactive gases combined with UV light, wherein timing of the reactive gases in the UV light is controlled;

depositing a second layer on the modified first layer;
forming a dielectric cap layer over the semiconductor substrate; and
etching one or more air gaps to a selected depth within the dielectric layer.

2. The method of claim 1 , wherein the first layer is deposited on the top surface of the one or more conductors by a selective metal deposition process, and wherein the first layer is in adhesive contact with the top surface of the one or more conductors.

3. The method of claim 1 , wherein the second layer is deposited on the top surface of the first layer by a deposition process, and wherein the second layer is in adhesive contact with the first layer.

4. The method of claim 1 , wherein the step of depositing the first layer on the top surface of the one or more conductors and the step of depositing the second layer on the first layer comprise one or more of: a second selective CVD, an electroless metal deposition, and a liquid phase deposition.

5. The method of claim 1 , wherein the first layer and the second layer form a bilayer cap, and wherein the bilayer cap is self-aligned.

6. The method of claim 1 , wherein the step of depositing the first layer on the top surface of the one or more conductors occurs as a continuous process with the step of depositing the second layer on the first layer.

7. A method for forming a semiconductor air gap structure, the method comprising:
providing a semiconductor substrate with one or more Cu conductors within a dielectric layer, wherein the one or more Cu conductors have a top surface;
depositing a first layer on the top surface of the one or more Cu conductors;
creating a second layer on the first layer, wherein creating the second layer comprises a modification of the top surface of the first layer by one or more of:
a thermal process using reactive gases, wherein timing of exposure to the reactive gases is controlled;
a direct plasma process using the reactive gases, wherein timing of the direct plasma process using the reactive gases is controlled; and
introducing the reactive gases combined with UV light, wherein timing of the reactive gases in the UV light is controlled;

forming a dielectric cap layer over the semiconductor substrate; and
etching one or more air gaps to a selected depth within the dielectric layer, wherein the selected depth corresponds to a bottom surface of the Cu conductors.

8. The method of claim 7 , wherein the thermal process using reactive gasses comprises:
heating the semiconductor substrate to a temperature from 350° C. to 400° C.;
exposing the top surface of the first layer to one or more reactive gases; and
holding the semiconductor substrate at said temperature for 15 seconds to 300 seconds.

9. The method of claim 7 , wherein the direct plasma process using reactive gases comprises:
using a plasma modification process, wherein a plasma power is between 100 W and 400 W;
exposing the semiconductor substrate to one or more reactive gases; and
holding the semiconductor substrate at said plasma power for 5 seconds to 60 seconds.

10. The method of claim 7 , wherein the reactive gases include one or more of: N 2 , NH 3 , ethylene (C 2 H 4 ), trimethylsilane, tetramethylsilane, dimethylsilane, dimethyl silacyclopentane, cyclic silazanes, trisilylamine (TSA), disilane, silane, cyclic hydrocarbons, linear hydrocarbons, and silicon substituted cyclic hydrocarbons.

11. The method of claim 7 , wherein the step of etching the one or more air gaps to the selected depth within the dielectric layer, comprises etching the one or more air gaps in the dielectric layer to a depth from 2 nm to 50 nm.

12. The method of claim 7 , wherein the step of depositing the first layer on the top surface of the one or more Cu conductors, the step of depositing the second layer on the first layer, and the step of forming the dielectric cap layer over the semiconductor substrate, are performed in a single process tool without air exposure between said steps.

Assignees

• IBM

Inventors

• Gates Stephen M
• Huang Elbert E
• Kioussis Dimitri R
• Penny Christopher J
• Priyadarshini Deepika

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/46

  using a liquid · CPC title

• H10P14/43

  Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

• H10W20/0526

  by thermal treatment thereof · CPC title

• H10W20/0523

  by irradiating with ultraviolet or particle radiation · CPC title