Device for high-K and metal gate stacks

Patent metadata

Field	Value
Publication number	US-9711415-B2
Application number	US-201213469645-A
Country	US
Kind code	B2
Filing date	May 11, 2012
Priority date	May 11, 2012
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate;
isolation features to separate different regions on the substrate;
a p-type field-effect transistor (pFET) core region having a first gate stack on the substrate, the first gate stack including an interfacial layer, a high k (HK) dielectric layer, and a capping layer of a first material and a capping layer of a second material disposed between the interfacial layer and the HK dielectric layer, the first material comprises a p-type metal oxide and the second material comprises an n-type metal oxide, and wherein the capping layer of the second material is directly on the capping layer of the first material and wherein the capping layer of the first material and the capping layer of the second material have a combined first thickness, and wherein the capping layer of the second material in the pFET core region has a first capping layer thickness;
an input/output pFET (pFET IO) region having a second gate stack on the substrate, the second gate stack including an interfacial layer, a HK dielectric layer, and a capping layer of the first material between the interfacial layer and the HK dielectric layer, wherein the interfacial layer of the second gate stack has a thickness that is greater than a thickness of the interfacial layer in the first gate stack, and wherein a capping layer of the second material in the pFET region has a second capping layer thickness that is smaller than the first capping layer thickness;
an n-type field-effect transistor (nFET) core region having a third gate stack on the substrate, the third gate stack including an interfacial layer, a HK dielectric layer directly on a capping layer of the second material, and wherein the capping layer of the second material in the nFET core region has a third capping layer thickness that is equal to the combined first thickness;
an input/output nFET (nFET IO) region having a fourth gate stack on the substrate, the fourth gate stack including an interfacial layer, a capping layer of the second material on the interfacial layer, and a HK dielectric layer directly on the capping layer of the second material, wherein the capping layer of the second material in the nFET IO region has a fourth capping layer thickness that is greater than the first capping layer thickness and smaller than the third capping layer thickness; and
a high-resistor region having a fifth gate stack on the substrate, the fifth gate stack including an interfacial layer, a capping layer of the second material on the interfacial layer, and a HK dielectric layer directly on the capping layer of the second material.

2. The device of claim 1 , wherein the second gate stack further comprises a capping layer of the second material above the capping layer of the first material.

3. The device of claim 2 , wherein the HK dielectric layer of the second gate stack is above the capping layer of the second material.

4. The semiconductor device of claim 2 , wherein a thickness of the capping layer of the second material in the fourth gate stack is equal to a combined thickness of the capping layers of the first and second materials in the second gate stack.

5. The device of claim 1 , wherein the p-type metal oxide comprises MgO, CaO, or mixtures thereof, and the n-type metal oxide comprises SrO, BaO, LaAlO 3 , Gd 2 O 3 , or mixtures thereof.

6. The device of claim 1 , wherein the first material comprises MgO, CaO, or mixtures thereof and the second material is BaO.

7. The device of claim 1 , wherein each of the second and fourth gate stacks is wider than each of the first and third gate stacks.

8. A semiconductor device, comprising:
a semiconductor substrate;
isolation features to separate different regions on the substrate;
a p-type field-effect transistor (pFET) core region having a first gate stack on the substrate, the first gate stack including an interfacial layer, a high k (HK) dielectric layer, and a capping layer of a first material and a capping layer of a second material disposed between the interfacial layer and the HK dielectric layer, and wherein the capping layer of the second material is directly on the capping layer of the first material and wherein the capping layer of the first material and the capping layer of the second material have a combined first thickness, and wherein the capping layer of the second material in the pFET core region has a first capping layer thickness;
an input/output pFET (pFET IO) region having a second gate stack on the substrate, the second gate stack including an interfacial layer, a HK dielectric layer, and a capping layer of the first material between the interfacial layer and the HK dielectric layer, wherein the interfacial layer of the second gate stack has a thickness that is greater than a thickness of the interfacial layer in the first gate stack, and wherein a capping layer of the second material in the pFET TO region has a second capping layer thickness that is smaller than the first capping layer thickness;
an n-type field-effect transistor (nFET) core region having a third gate stack on the substrate, the third gate stack including an interfacial layer, a HK dielectric layer directly on a capping layer of the second material, and wherein the capping layer of the second material in the nFET core region has a third capping layer thickness that is equal to the combined first thickness;
an input/output nFET (nFET TO) region having a fourth gate stack on the substrate, the fourth gate stack including an interfacial layer, a capping layer of the second material on the interfacial layer, and a HK dielectric layer directly on the capping layer of the second material, wherein the capping layer of the second material in the nFET TO region has a fourth capping layer thickness that is greater than the first capping layer thickness and smaller than the third capping layer thickness; and
a high-resistor region having a fifth gate stack on the substrate, the fifth gate stack including an interfacial layer, a capping layer of the second material on the interfacial layer, and a HK dielectric layer directly on the capping layer of the second material,
wherein in both the pFET TO and pFET core regions, the capping layer of the second material is disposed between the capping layer of the first material and the HK layer such that the capping layer of the first material and the HK layer are not in direct contact.

9. A semiconductor device, comprising:
a semiconductor substrate having regions for a core p-type field-effect transistor (pFET) region and an input/output pFET (pFET TO) region;
an interfacial layer on the substrate in each of the pFET TO region and the pFET core region;
in the pFET TO region, a capping layer of a first material on the interfacial layer and a capping layer of a second material on the interfacial layer and directly on the capping layer of the first material, the capping layers of the first and second materials in the pFET TO region having a first combined thickness, wherein the capping layer of the second material in the pFET TO region has a first capping layer thickness;
in the pFET core region, a capping layer of the first material on the interfacial layer and a capping layer of the second material on the interfacial layer and directly on the capping layer of the first material, the capping layers of the first and second materials in the pFET core region having a second combined thickness that is different than from the first combined thickness, wherein the capping layer of the second material in the pFET core region has a second capping layer thickness that is greater than the first capping layer thickness;
in both the pFET TO region and the pFET core region, a high-k (HK)

Assignees

• Lin Jyun-Ming
• Wu Wei Cheng
• Chung Sheng-Chen
• Young Bao-Ru
• Chuang Hak-Lay
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Jyun-Ming
• Wu Wei Cheng
• Chung Sheng-Chen
• Young Bao-Ru
• Chuang Hak-Lay

Classifications

• H01L21/823857

  Electricity · mapped topic

• H01L21/823842 Primary

  Electricity · mapped topic

• H10D84/0181

  Manufacturing their gate insulating layers · CPC title

• H10D84/0177 Primary

  the gate conductors having different materials or different implants · CPC title

• H10D84/038 Primary

  using silicon technology, e.g. SiGe · CPC title