Field emission devices and methods of making thereof

Patent metadata

Field	Value
Publication number	US-9711392-B2
Application number	US-201213558265-A
Country	US
Kind code	B2
Filing date	Jul 25, 2012
Priority date	Jul 25, 2012
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

In one embodiment of the present invention, an electronic device includes a first emitter/collector region and a second emitter/collector region disposed in a substrate. The first emitter/collector region has a first edge/tip, and the second emitter/collector region has a second edge/tip. A gap separates the first edge/tip from the second edge/tip. The first emitter/collector region, the second emitter/collector region, and the gap form a field emission device.

First claim

What is claimed is:

1. A semiconductor device comprising an electrostatic discharge protection device, the electrostatic discharge protection device comprising:
an array of field emission devices disposed in a semiconductor substrate, the array of field emission device being coupled in parallel with each other and providing a plurality of parallel discharge paths, wherein each field emission device of the array of field emission devices comprises:
a first emitter/collector region disposed in the semiconductor substrate, the first emitter/collector region having a first edge/tip,
a second emitter/collector region disposed in the semiconductor substrate, the second emitter/collector region having a second edge/tip, and
a hermetically sealed gap separating the first edge/tip from the second edge/tip, the first emitter/collector region, the second emitter/collector region, and the gap forming the first field emission device of the array of field emission devices for conducting a portion of the electrostatic discharge (ESD), wherein the first field emission device conducts by an electrostatic emission through the gap, wherein the conduction through the gap completes an electrical connection between the first emitter/collector region and the second emitter/collector region for discharging an ESD pulse;

a plurality of first contact regions disposed at a first major surface of the semiconductor substrate over the first emitter/collector region of each of the array of field emission devices, wherein each of the plurality of first contact regions is coupled to a corresponding one of the adjacent first emitter/collector region; and
a common contact region disposed at an opposite second major surface of the substrate, the common contact region coupled to the second emitter/collector region.

2. The device of claim 1 , further comprising:
a third emitter/collector region disposed in the substrate, the third emitter/collector region having a third edge/tip;
a fourth emitter/collector region disposed in the substrate, the fourth emitter/collector region having a fourth edge/tip; and
a second gap separating the third edge/tip from the fourth edge/tip, the third emitter/collector region, the fourth emitter/collector region, and the second gap forming a second field emission device, wherein the first field emission device and the second field emission device form part of the array of field emission devices.

3. The device of claim 1 , wherein the first edge/tip and the second edge/tip are pointed tip regions.

4. The device of claim 1 , wherein the first edge/tip and the second edge/tip are wedge shaped regions.

5. The device of claim 1 , wherein the first edge/tip and the second edge/tip point towards each other.

6. The device of claim 1 , wherein the first edge/tip and the second edge/tip have about the same length, and wherein a length of the first edge/tip is about 0.5 μm to about 1 mm.

7. The device of claim 1 , wherein the semiconductor substrate comprises silicon.

8. A semiconductor device comprising an electrostatic discharge protection device, the electrostatic discharge protection device comprising:
an array of field emission devices disposed in a semiconductor substrate, the array of field emission device being coupled in parallel with each other and providing a plurality of parallel discharge paths, wherein each field emission device of the array of field emission devices comprises:
a first trench disposed in the semiconductor substrate;
a first cavity disposed in the semiconductor substrate under the first trench;
a first insulating liner disposed on a sidewall of the first trench and extending into the first cavity;
a second trench proximate the first trench;
a second cavity disposed in the substrate under the second trench, wherein the first cavity intersects the second cavity at a first edge/tip and a second edge/tip;
a second insulating liner disposed on a sidewall of the second trench and extending into the second cavity, wherein the first edge/tip is isolated from adjacent first edge/tips other than the second edge/tip by the first and the second insulating liners, and wherein the first edge/tip and the second edge/tip form part of the field emission device;

a plurality of first contact regions disposed at a first major surface of the semiconductor substrate over each of the first edge/tip of each of the array of field emission devices, wherein each of the plurality of first contact regions is coupled to a corresponding one of the adjacent first edge/tips; and
a common contact region disposed at an opposite second major surface of the substrate, the common contact region coupled to the second edge/tip.

9. The device of claim 8 , further comprising:
a capping layer sealing the first trench and the second trench.

10. The device of claim 8 , wherein the first cavity and the second cavity comprise balloon shaped sidewalls.

11. The device of claim 8 , wherein the first edge/tip and the second edge/tip are wedge shaped regions.

12. The device of claim 8 , wherein the semiconductor substrate comprises silicon.

13. The device of claim 8 , further comprising:
a leadframe comprising a plurality of leads supporting the field emission device;
a bond wire coupling the field emission device with a lead of the leadframe; and
an encapsulant disposed at the leadframe and the field emission device.

14. The device of claim 8 , further comprising:
a leadless frame supporting the field emission device;
a bond wire coupling the field emission device with the leadless frame; and
an encapsulant disposed at the leadless frame and the field emission device.

15. The device of claim 8 , further comprising:
a can disposed over the field emission device;
a laminated board disposed under the field emission device, wherein the field emission device is disposed between the can and the laminated board; and
an encapsulant disposed at the field emission device.

16. The device of claim 8 , further comprising:
a laminated board coupled to contacts of the field emission device; and
an encapsulant disposed at the laminated board and the field emission device, wherein the laminated board and the encapsulant hermetically seal the first cavity and the second cavity.

17. A method of forming an electronic device, the method comprising:
forming an electrostatic discharge protection device by:
forming an array of field emission devices in a semiconductor substrate;
connecting the array of field emission devices in parallel and providing a plurality of parallel discharge paths for electrostatic discharge, wherein forming each field emission device of the array of field emission devices further comprises
forming a first trench and a second trench in the semiconductor substrate;
forming a first edge/tip and a second edge/tip by forming a first cavity under the first trench and a second cavity under the second trench, wherein the first cavity intersects with the second cavity to form the first edge/tip and the second edge/tip, wherein the first edge/tip is opposite the second edge/tip, and wherein the first edge/tip and the second edge/tip form part of a first field emission device; and
forming first isolation liner on sidewalls of the first trench and a second isolation liner on sidewalls of the second trench, wherein the first isolation liner extends into the first cavity past the first edge/tip and the second isolation liner extends into the second cavity past the first edge/tip, wherein the first edge/tip is isolated from adjacent edge/tips other than the second edge/tip by the

Assignees

• Dehe Alfons
• Sojka Damian
• Schmenn Andre
• Ahrens Carsten
• Infineon Technologies Ag

Inventors

• Dehe Alfons
• Sojka Damian
• Schmenn Andre
• Ahrens Carsten

Classifications

• H10P95/08

  Planarisation of organic insulating materials · CPC title

• H10P50/286

  of organic materials · CPC title

• H10P50/282

  of inorganic materials · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title